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VGAansturing 1
Aansturing van een vga scherm dmv een STM32F407GTx
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Macros | |
| #define | ADC_SR_AWD ((uint8_t)0x01) |
| #define | ADC_SR_EOC ((uint8_t)0x02) |
| #define | ADC_SR_JEOC ((uint8_t)0x04) |
| #define | ADC_SR_JSTRT ((uint8_t)0x08) |
| #define | ADC_SR_STRT ((uint8_t)0x10) |
| #define | ADC_SR_OVR ((uint8_t)0x20) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR1_RES ((uint32_t)0x03000000) |
| #define | ADC_CR1_RES_0 ((uint32_t)0x01000000) |
| #define | ADC_CR1_RES_1 ((uint32_t)0x02000000) |
| #define | ADC_CR1_OVRIE ((uint32_t)0x04000000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_DDS ((uint32_t)0x00000200) |
| #define | ADC_CR2_EOCS ((uint32_t)0x00000400) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
| #define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
| #define | ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
| #define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
| #define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
| #define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
| #define | ADC_CR2_EXTEN ((uint32_t)0x30000000) |
| #define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | ADC_CSR_AWD1 ((uint32_t)0x00000001) |
| #define | ADC_CSR_EOC1 ((uint32_t)0x00000002) |
| #define | ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
| #define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
| #define | ADC_CSR_STRT1 ((uint32_t)0x00000010) |
| #define | ADC_CSR_DOVR1 ((uint32_t)0x00000020) |
| #define | ADC_CSR_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_CSR_EOC2 ((uint32_t)0x00000200) |
| #define | ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
| #define | ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
| #define | ADC_CSR_STRT2 ((uint32_t)0x00001000) |
| #define | ADC_CSR_DOVR2 ((uint32_t)0x00002000) |
| #define | ADC_CSR_AWD3 ((uint32_t)0x00010000) |
| #define | ADC_CSR_EOC3 ((uint32_t)0x00020000) |
| #define | ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
| #define | ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
| #define | ADC_CSR_STRT3 ((uint32_t)0x00100000) |
| #define | ADC_CSR_DOVR3 ((uint32_t)0x00200000) |
| #define | ADC_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC_CCR_DDS ((uint32_t)0x00002000) |
| #define | ADC_CCR_DMA ((uint32_t)0x0000C000) |
| #define | ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
| #define | ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
| #define | ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
| #define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
| #define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
| #define | ADC_CCR_VBATE ((uint32_t)0x00400000) |
| #define | ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
| #define | ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint8_t)0x01) |
| #define | CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
| #define | CRYP_CR_ALGOMODE ((uint32_t)0x00000038) |
| #define | CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
| #define | CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
| #define | CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
| #define | CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
| #define | CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
| #define | CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
| #define | CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
| #define | CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
| #define | CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
| #define | CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
| #define | CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
| #define | CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
| #define | CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
| #define | CRYP_SR_IFEM ((uint32_t)0x00000001) |
| #define | CRYP_SR_IFNF ((uint32_t)0x00000002) |
| #define | CRYP_SR_OFNE ((uint32_t)0x00000004) |
| #define | CRYP_SR_OFFU ((uint32_t)0x00000008) |
| #define | CRYP_SR_BUSY ((uint32_t)0x00000010) |
| #define | CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
| #define | CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
| #define | CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
| #define | CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
| #define | CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
| #define | CRYP_RISR_INRIS ((uint32_t)0x00000002) |
| #define | CRYP_MISR_INMIS ((uint32_t)0x00000001) |
| #define | CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
| #define | DCMI_CR_CM ((uint32_t)0x00000002) |
| #define | DCMI_CR_CROP ((uint32_t)0x00000004) |
| #define | DCMI_CR_JPEG ((uint32_t)0x00000008) |
| #define | DCMI_CR_ESS ((uint32_t)0x00000010) |
| #define | DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
| #define | DCMI_CR_HSPOL ((uint32_t)0x00000040) |
| #define | DCMI_CR_VSPOL ((uint32_t)0x00000080) |
| #define | DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
| #define | DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
| #define | DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
| #define | DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
| #define | DCMI_CR_CRE ((uint32_t)0x00001000) |
| #define | DCMI_CR_ENABLE ((uint32_t)0x00004000) |
| #define | DCMI_SR_HSYNC ((uint32_t)0x00000001) |
| #define | DCMI_SR_VSYNC ((uint32_t)0x00000002) |
| #define | DCMI_SR_FNE ((uint32_t)0x00000004) |
| #define | DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) |
| #define | DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) |
| #define | DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) |
| #define | DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) |
| #define | DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) |
| #define | DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
| #define | DCMI_IER_OVF_IE ((uint32_t)0x00000002) |
| #define | DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
| #define | DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
| #define | DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
| #define | DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) |
| #define | DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) |
| #define | DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) |
| #define | DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) |
| #define | DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) |
| #define | DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
| #define | DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) |
| #define | DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
| #define | DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
| #define | DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
| #define | DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
| #define | DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
| #define | DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
| #define | DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
| #define | DMA_SxCR_MBURST ((uint32_t)0x01800000) |
| #define | DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
| #define | DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
| #define | DMA_SxCR_PBURST ((uint32_t)0x00600000) |
| #define | DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
| #define | DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
| #define | DMA_SxCR_ACK ((uint32_t)0x00100000) |
| #define | DMA_SxCR_CT ((uint32_t)0x00080000) |
| #define | DMA_SxCR_DBM ((uint32_t)0x00040000) |
| #define | DMA_SxCR_PL ((uint32_t)0x00030000) |
| #define | DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
| #define | DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
| #define | DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
| #define | DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
| #define | DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
| #define | DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
| #define | DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
| #define | DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
| #define | DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
| #define | DMA_SxCR_MINC ((uint32_t)0x00000400) |
| #define | DMA_SxCR_PINC ((uint32_t)0x00000200) |
| #define | DMA_SxCR_CIRC ((uint32_t)0x00000100) |
| #define | DMA_SxCR_DIR ((uint32_t)0x000000C0) |
| #define | DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
| #define | DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
| #define | DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
| #define | DMA_SxCR_TCIE ((uint32_t)0x00000010) |
| #define | DMA_SxCR_HTIE ((uint32_t)0x00000008) |
| #define | DMA_SxCR_TEIE ((uint32_t)0x00000004) |
| #define | DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
| #define | DMA_SxCR_EN ((uint32_t)0x00000001) |
| #define | DMA_SxNDT ((uint32_t)0x0000FFFF) |
| #define | DMA_SxNDT_0 ((uint32_t)0x00000001) |
| #define | DMA_SxNDT_1 ((uint32_t)0x00000002) |
| #define | DMA_SxNDT_2 ((uint32_t)0x00000004) |
| #define | DMA_SxNDT_3 ((uint32_t)0x00000008) |
| #define | DMA_SxNDT_4 ((uint32_t)0x00000010) |
| #define | DMA_SxNDT_5 ((uint32_t)0x00000020) |
| #define | DMA_SxNDT_6 ((uint32_t)0x00000040) |
| #define | DMA_SxNDT_7 ((uint32_t)0x00000080) |
| #define | DMA_SxNDT_8 ((uint32_t)0x00000100) |
| #define | DMA_SxNDT_9 ((uint32_t)0x00000200) |
| #define | DMA_SxNDT_10 ((uint32_t)0x00000400) |
| #define | DMA_SxNDT_11 ((uint32_t)0x00000800) |
| #define | DMA_SxNDT_12 ((uint32_t)0x00001000) |
| #define | DMA_SxNDT_13 ((uint32_t)0x00002000) |
| #define | DMA_SxNDT_14 ((uint32_t)0x00004000) |
| #define | DMA_SxNDT_15 ((uint32_t)0x00008000) |
| #define | DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
| #define | DMA_SxFCR_FS ((uint32_t)0x00000038) |
| #define | DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
| #define | DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
| #define | DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
| #define | DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
| #define | DMA_SxFCR_FTH ((uint32_t)0x00000003) |
| #define | DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
| #define | DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
| #define | DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
| #define | DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| #define | FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| #define | FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| #define | FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
| #define | FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
| #define | FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
| #define | FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| #define | FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| #define | FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| #define | FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| #define | FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| #define | FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
| #define | FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000001) |
| #define | FLASH_SR_SOP ((uint32_t)0x00000002) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| #define | FLASH_SR_PGPERR ((uint32_t)0x00000040) |
| #define | FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| #define | FLASH_SR_BSY ((uint32_t)0x00010000) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_SER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
| #define | FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
| #define | FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
| #define | FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
| #define | FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | FLASH_CR_STRT ((uint32_t)0x00010000) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| #define | FLASH_CR_LOCK ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
| #define | FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
| #define | FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
| #define | FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
| #define | FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
| #define | FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
| #define | FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
| #define | FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
| #define | FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
| #define | FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
| #define | FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
| #define | FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
| #define | FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
| #define | FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
| #define | FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
| #define | FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
| #define | FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
| #define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR1_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR1_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR2_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR2_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR3_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR3_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR4_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR4_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR2_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR2_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR2_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR2_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR2_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR2_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR3_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR3_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR3_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR3_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR3_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR3_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR4_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR4_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR4_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR4_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR4_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR4_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SR2_IRS ((uint8_t)0x01) |
| #define | FSMC_SR2_ILS ((uint8_t)0x02) |
| #define | FSMC_SR2_IFS ((uint8_t)0x04) |
| #define | FSMC_SR2_IREN ((uint8_t)0x08) |
| #define | FSMC_SR2_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR2_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR2_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR3_IRS ((uint8_t)0x01) |
| #define | FSMC_SR3_ILS ((uint8_t)0x02) |
| #define | FSMC_SR3_IFS ((uint8_t)0x04) |
| #define | FSMC_SR3_IREN ((uint8_t)0x08) |
| #define | FSMC_SR3_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR3_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR3_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR4_IRS ((uint8_t)0x01) |
| #define | FSMC_SR4_ILS ((uint8_t)0x02) |
| #define | FSMC_SR4_IFS ((uint8_t)0x04) |
| #define | FSMC_SR4_IREN ((uint8_t)0x08) |
| #define | FSMC_SR4_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR4_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR4_FEMPT ((uint8_t)0x40) |
| #define | FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| #define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| #define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| #define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| #define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| #define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| #define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| #define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| #define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| #define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| #define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| #define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| #define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| #define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| #define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| #define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| #define | GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| #define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| #define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| #define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| #define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| #define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| #define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| #define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| #define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| #define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| #define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| #define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| #define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| #define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| #define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| #define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | HASH_CR_INIT ((uint32_t)0x00000004) |
| #define | HASH_CR_DMAE ((uint32_t)0x00000008) |
| #define | HASH_CR_DATATYPE ((uint32_t)0x00000030) |
| #define | HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
| #define | HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
| #define | HASH_CR_MODE ((uint32_t)0x00000040) |
| #define | HASH_CR_ALGO ((uint32_t)0x00000080) |
| #define | HASH_CR_NBW ((uint32_t)0x00000F00) |
| #define | HASH_CR_NBW_0 ((uint32_t)0x00000100) |
| #define | HASH_CR_NBW_1 ((uint32_t)0x00000200) |
| #define | HASH_CR_NBW_2 ((uint32_t)0x00000400) |
| #define | HASH_CR_NBW_3 ((uint32_t)0x00000800) |
| #define | HASH_CR_DINNE ((uint32_t)0x00001000) |
| #define | HASH_CR_LKEY ((uint32_t)0x00010000) |
| #define | HASH_STR_NBW ((uint32_t)0x0000001F) |
| #define | HASH_STR_NBW_0 ((uint32_t)0x00000001) |
| #define | HASH_STR_NBW_1 ((uint32_t)0x00000002) |
| #define | HASH_STR_NBW_2 ((uint32_t)0x00000004) |
| #define | HASH_STR_NBW_3 ((uint32_t)0x00000008) |
| #define | HASH_STR_NBW_4 ((uint32_t)0x00000010) |
| #define | HASH_STR_DCAL ((uint32_t)0x00000100) |
| #define | HASH_IMR_DINIM ((uint32_t)0x00000001) |
| #define | HASH_IMR_DCIM ((uint32_t)0x00000002) |
| #define | HASH_SR_DINIS ((uint32_t)0x00000001) |
| #define | HASH_SR_DCIS ((uint32_t)0x00000002) |
| #define | HASH_SR_DMAS ((uint32_t)0x00000004) |
| #define | HASH_SR_BUSY ((uint32_t)0x00000008) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | PWR_CR_LPDS ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CR_FPDS ((uint16_t)0x0200) |
| #define | PWR_CR_VOS ((uint16_t)0x4000) |
| #define | PWR_CR_PMODE PWR_CR_VOS |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_BRR ((uint16_t)0x0008) |
| #define | PWR_CSR_EWUP ((uint16_t)0x0100) |
| #define | PWR_CSR_BRE ((uint16_t)0x0200) |
| #define | PWR_CSR_VOSRDY ((uint16_t)0x4000) |
| #define | PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008 |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010 |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020 |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040 |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080 |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100 |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200 |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400 |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800 |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000 |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000 |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000 |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000 |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
| #define | RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
| #define | RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
| #define | RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
| #define | RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
| #define | RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
| #define | RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
| #define | RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
| #define | RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
| #define | RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
| #define | RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
| #define | RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| #define | RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
| #define | RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
| #define | RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| #define | RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
| #define | RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
| #define | RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
| #define | RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
| #define | RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
| #define | RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
| #define | RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
| #define | RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
| #define | RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
| #define | RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
| #define | RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| #define | RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
| #define | RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
| #define | RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
| #define | RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) |
| #define | RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
| #define | RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
| #define | RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020) |
| #define | RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
| #define | RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| #define | RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
| #define | RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
| #define | RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
| #define | RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
| #define | RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
| #define | RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
| #define | RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
| #define | RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
| #define | RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
| #define | RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| #define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| #define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
| #define | RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
| #define | RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
| #define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| #define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| #define | RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
| #define | RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
| #define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| #define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
| #define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
| #define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
| #define | RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
| #define | RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
| #define | RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
| #define | RNG_CR_RNGEN ((uint32_t)0x00000004) |
| #define | RNG_CR_IE ((uint32_t)0x00000008) |
| #define | RNG_SR_DRDY ((uint32_t)0x00000001) |
| #define | RNG_SR_CECS ((uint32_t)0x00000002) |
| #define | RNG_SR_SECS ((uint32_t)0x00000004) |
| #define | RNG_SR_CEIS ((uint32_t)0x00000020) |
| #define | RNG_SR_SEIS ((uint32_t)0x00000040) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| #define | RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
| #define | RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) |
| #define | SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
| #define | SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
| #define | TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
| #define | TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
| #define | TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
| #define | TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
| #define | TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040 |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080 |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| #define | DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
| #define | ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| #define | ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| #define | ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| #define | ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| #define | ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| #define | ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| #define | ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| #define | ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| #define | ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| #define | ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| #define | ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| #define | ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| #define | ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| #define | ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| #define | ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| #define | ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| #define | ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| #define | ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| #define | ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| #define | ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| #define | ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| #define | ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| #define | ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| #define | ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| #define | ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| #define | ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| #define | ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
| #define | ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
| #define | ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| #define | ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
| #define | ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
| #define | ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
| #define | ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
| #define | ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
| #define | ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
| #define | ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
| #define | ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
| #define | ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
| #define | ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| #define | ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
| #define | ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
| #define | ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
| #define | ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| #define | ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| #define | ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| #define | ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| #define | ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| #define | ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| #define | ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| #define | ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
ADCPRE[1:0] bits (ADC prescaler)
Definition at line 1585 of file stm32f4xx.h.
| #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 1586 of file stm32f4xx.h.
| #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 1587 of file stm32f4xx.h.
| #define ADC_CCR_DDS ((uint32_t)0x00002000) |
DMA disable selection (Multi-ADC mode)
Definition at line 1581 of file stm32f4xx.h.
| #define ADC_CCR_DELAY ((uint32_t)0x00000F00) |
DELAY[3:0] bits (Delay between 2 sampling phases)
Definition at line 1576 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 1577 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 1578 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 1579 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 1580 of file stm32f4xx.h.
| #define ADC_CCR_DMA ((uint32_t)0x0000C000) |
DMA[1:0] bits (Direct Memory Access mode for multimode)
Definition at line 1582 of file stm32f4xx.h.
| #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
Bit 0
Definition at line 1583 of file stm32f4xx.h.
| #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
Bit 1
Definition at line 1584 of file stm32f4xx.h.
| #define ADC_CCR_MULTI ((uint32_t)0x0000001F) |
MULTI[4:0] bits (Multi-ADC mode selection)
Definition at line 1570 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1571 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1572 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1573 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1574 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1575 of file stm32f4xx.h.
| #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
Definition at line 1589 of file stm32f4xx.h.
| #define ADC_CCR_VBATE ((uint32_t)0x00400000) |
VBAT Enable
Definition at line 1588 of file stm32f4xx.h.
| #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
1st data of a pair of regular conversions
Definition at line 1592 of file stm32f4xx.h.
| #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
2nd data of a pair of regular conversions
Definition at line 1593 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
Definition at line 1248 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1249 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1250 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1251 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1252 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1253 of file stm32f4xx.h.
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
Definition at line 1267 of file stm32f4xx.h.
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
AAnalog Watchdog interrupt enable
Definition at line 1255 of file stm32f4xx.h.
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
Definition at line 1258 of file stm32f4xx.h.
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
Definition at line 1260 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
Definition at line 1262 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 1263 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 1264 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 1265 of file stm32f4xx.h.
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
Definition at line 1254 of file stm32f4xx.h.
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
Definition at line 1259 of file stm32f4xx.h.
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
Definition at line 1266 of file stm32f4xx.h.
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
Definition at line 1261 of file stm32f4xx.h.
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
Definition at line 1256 of file stm32f4xx.h.
| #define ADC_CR1_OVRIE ((uint32_t)0x04000000) |
overrun interrupt enable
Definition at line 1271 of file stm32f4xx.h.
| #define ADC_CR1_RES ((uint32_t)0x03000000) |
RES[2:0] bits (Resolution)
Definition at line 1268 of file stm32f4xx.h.
| #define ADC_CR1_RES_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 1269 of file stm32f4xx.h.
| #define ADC_CR1_RES_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 1270 of file stm32f4xx.h.
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
Definition at line 1257 of file stm32f4xx.h.
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
Definition at line 1274 of file stm32f4xx.h.
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
Definition at line 1279 of file stm32f4xx.h.
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
Definition at line 1275 of file stm32f4xx.h.
| #define ADC_CR2_DDS ((uint32_t)0x00000200) |
DMA disable selection (Single ADC)
Definition at line 1277 of file stm32f4xx.h.
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
Definition at line 1276 of file stm32f4xx.h.
| #define ADC_CR2_EOCS ((uint32_t)0x00000400) |
End of conversion selection
Definition at line 1278 of file stm32f4xx.h.
| #define ADC_CR2_EXTEN ((uint32_t)0x30000000) |
EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)
Definition at line 1294 of file stm32f4xx.h.
| #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 1295 of file stm32f4xx.h.
| #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 1296 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
EXTSEL[3:0] bits (External Event Select for regular group)
Definition at line 1289 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 1290 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 1291 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 1292 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 1293 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)
Definition at line 1285 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 1286 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 1287 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
JEXTSEL[3:0] bits (External event select for injected group)
Definition at line 1280 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 1281 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 1282 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 1283 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 1284 of file stm32f4xx.h.
| #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
Start Conversion of injected channels
Definition at line 1288 of file stm32f4xx.h.
| #define ADC_CR2_SWSTART ((uint32_t)0x40000000) |
Start Conversion of regular channels
Definition at line 1297 of file stm32f4xx.h.
| #define ADC_CSR_AWD1 ((uint32_t)0x00000001) |
ADC1 Analog watchdog flag
Definition at line 1550 of file stm32f4xx.h.
| #define ADC_CSR_AWD2 ((uint32_t)0x00000100) |
ADC2 Analog watchdog flag
Definition at line 1556 of file stm32f4xx.h.
| #define ADC_CSR_AWD3 ((uint32_t)0x00010000) |
ADC3 Analog watchdog flag
Definition at line 1562 of file stm32f4xx.h.
| #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) |
ADC1 DMA overrun flag
Definition at line 1555 of file stm32f4xx.h.
| #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) |
ADC2 DMA overrun flag
Definition at line 1561 of file stm32f4xx.h.
| #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) |
ADC3 DMA overrun flag
Definition at line 1567 of file stm32f4xx.h.
| #define ADC_CSR_EOC1 ((uint32_t)0x00000002) |
ADC1 End of conversion
Definition at line 1551 of file stm32f4xx.h.
| #define ADC_CSR_EOC2 ((uint32_t)0x00000200) |
ADC2 End of conversion
Definition at line 1557 of file stm32f4xx.h.
| #define ADC_CSR_EOC3 ((uint32_t)0x00020000) |
ADC3 End of conversion
Definition at line 1563 of file stm32f4xx.h.
| #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
ADC1 Injected channel end of conversion
Definition at line 1552 of file stm32f4xx.h.
| #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
ADC2 Injected channel end of conversion
Definition at line 1558 of file stm32f4xx.h.
| #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
ADC3 Injected channel end of conversion
Definition at line 1564 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
ADC1 Injected channel Start flag
Definition at line 1553 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
ADC2 Injected channel Start flag
Definition at line 1559 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
ADC3 Injected channel Start flag
Definition at line 1565 of file stm32f4xx.h.
| #define ADC_CSR_STRT1 ((uint32_t)0x00000010) |
ADC1 Regular channel Start flag
Definition at line 1554 of file stm32f4xx.h.
| #define ADC_CSR_STRT2 ((uint32_t)0x00001000) |
ADC2 Regular channel Start flag
Definition at line 1560 of file stm32f4xx.h.
| #define ADC_CSR_STRT3 ((uint32_t)0x00100000) |
ADC3 Regular channel Start flag
Definition at line 1566 of file stm32f4xx.h.
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
Definition at line 1547 of file stm32f4xx.h.
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
Definition at line 1546 of file stm32f4xx.h.
| #define ADC_HTR_HT ((uint16_t)0x0FFF) |
Analog watchdog high threshold
Definition at line 1392 of file stm32f4xx.h.
| #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 1534 of file stm32f4xx.h.
| #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 1537 of file stm32f4xx.h.
| #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 1540 of file stm32f4xx.h.
| #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 1543 of file stm32f4xx.h.
| #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
Data offset for injected channel 1
Definition at line 1380 of file stm32f4xx.h.
| #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
Data offset for injected channel 2
Definition at line 1383 of file stm32f4xx.h.
| #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
Data offset for injected channel 3
Definition at line 1386 of file stm32f4xx.h.
| #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
Data offset for injected channel 4
Definition at line 1389 of file stm32f4xx.h.
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
Definition at line 1529 of file stm32f4xx.h.
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 1530 of file stm32f4xx.h.
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 1531 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
Definition at line 1505 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1506 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1507 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1508 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1509 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1510 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
Definition at line 1511 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 1512 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 1513 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 1514 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 1515 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 1516 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
Definition at line 1517 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 1518 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 1519 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 1520 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 1521 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 1522 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
Definition at line 1523 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1524 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1525 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1526 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 1527 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 1528 of file stm32f4xx.h.
| #define ADC_LTR_LT ((uint16_t)0x0FFF) |
Analog watchdog low threshold
Definition at line 1395 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
Definition at line 1300 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1301 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1302 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1303 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
Definition at line 1304 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 1305 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 1306 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 1307 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
Definition at line 1308 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 1309 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 1310 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
Definition at line 1311 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
Definition at line 1312 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 1313 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 1314 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 1315 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
Definition at line 1316 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
Definition at line 1317 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
Definition at line 1318 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
Definition at line 1319 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
Definition at line 1320 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1321 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1322 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1323 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
Definition at line 1324 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
Definition at line 1325 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
Definition at line 1326 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
Definition at line 1327 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
Definition at line 1328 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
Definition at line 1329 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
Definition at line 1330 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
Definition at line 1331 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
SMP18[2:0] bits (Channel 18 Sample time selection)
Definition at line 1332 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 1333 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 1334 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 1335 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
Definition at line 1338 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1339 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1340 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1341 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
Definition at line 1342 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 1343 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 1344 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 1345 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
Definition at line 1346 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 1347 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 1348 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
Definition at line 1349 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
Definition at line 1350 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 1351 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 1352 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 1353 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
Definition at line 1354 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
Definition at line 1355 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
Definition at line 1356 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
Definition at line 1357 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
Definition at line 1358 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1359 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1360 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1361 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
Definition at line 1362 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
Definition at line 1363 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
Definition at line 1364 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
Definition at line 1365 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
Definition at line 1366 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
Definition at line 1367 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
Definition at line 1368 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
Definition at line 1369 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
Definition at line 1370 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 1371 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 1372 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 1373 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
Definition at line 1374 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
Definition at line 1375 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
Definition at line 1376 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
Definition at line 1377 of file stm32f4xx.h.
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
Definition at line 1422 of file stm32f4xx.h.
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 1423 of file stm32f4xx.h.
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 1424 of file stm32f4xx.h.
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 1425 of file stm32f4xx.h.
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 1426 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
Definition at line 1398 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1399 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1400 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1401 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1402 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1403 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
Definition at line 1404 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 1405 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 1406 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 1407 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 1408 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 1409 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
Definition at line 1410 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 1411 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 1412 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 1413 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 1414 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 1415 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
Definition at line 1416 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1417 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1418 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1419 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 1420 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 1421 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
Definition at line 1447 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1448 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1449 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1450 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 1451 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 1452 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
Definition at line 1453 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 1454 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 1455 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 1456 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 1457 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
Definition at line 1458 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
Definition at line 1459 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
Definition at line 1460 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
Definition at line 1461 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
Definition at line 1462 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
Definition at line 1463 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
Definition at line 1464 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
Definition at line 1429 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1430 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1431 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1432 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1433 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1434 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
Definition at line 1435 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 1436 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 1437 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 1438 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 1439 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 1440 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
Definition at line 1441 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 1442 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 1443 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 1444 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 1445 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 1446 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
Definition at line 1467 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 1468 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 1469 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 1470 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 1471 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 1472 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
Definition at line 1473 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 1474 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 1475 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 1476 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 1477 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 1478 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
Definition at line 1479 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 1480 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 1481 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 1482 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 1483 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 1484 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
Definition at line 1485 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 1486 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 1487 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 1488 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 1489 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 1490 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
Definition at line 1491 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 1492 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 1493 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 1494 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 1495 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
Definition at line 1496 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
Definition at line 1497 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
Definition at line 1498 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
Definition at line 1499 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
Definition at line 1500 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
Definition at line 1501 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
Definition at line 1502 of file stm32f4xx.h.
| #define ADC_SR_AWD ((uint8_t)0x01) |
Analog watchdog flag
Definition at line 1240 of file stm32f4xx.h.
| #define ADC_SR_EOC ((uint8_t)0x02) |
End of conversion
Definition at line 1241 of file stm32f4xx.h.
| #define ADC_SR_JEOC ((uint8_t)0x04) |
Injected channel end of conversion
Definition at line 1242 of file stm32f4xx.h.
| #define ADC_SR_JSTRT ((uint8_t)0x08) |
Injected channel Start flag
Definition at line 1243 of file stm32f4xx.h.
| #define ADC_SR_OVR ((uint8_t)0x20) |
Overrun flag
Definition at line 1245 of file stm32f4xx.h.
| #define ADC_SR_STRT ((uint8_t)0x10) |
Regular channel Start flag
Definition at line 1244 of file stm32f4xx.h.
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
Definition at line 1693 of file stm32f4xx.h.
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
Definition at line 1697 of file stm32f4xx.h.
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
Definition at line 1698 of file stm32f4xx.h.
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
Definition at line 1696 of file stm32f4xx.h.
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
Definition at line 1694 of file stm32f4xx.h.
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
Definition at line 1695 of file stm32f4xx.h.
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
Definition at line 1682 of file stm32f4xx.h.
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
Definition at line 1681 of file stm32f4xx.h.
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
Definition at line 1680 of file stm32f4xx.h.
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
Definition at line 1684 of file stm32f4xx.h.
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 1685 of file stm32f4xx.h.
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 1686 of file stm32f4xx.h.
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 1687 of file stm32f4xx.h.
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
Definition at line 1690 of file stm32f4xx.h.
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
Definition at line 1689 of file stm32f4xx.h.
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 1892 of file stm32f4xx.h.
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 1893 of file stm32f4xx.h.
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 1902 of file stm32f4xx.h.
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 1903 of file stm32f4xx.h.
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 1904 of file stm32f4xx.h.
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 1905 of file stm32f4xx.h.
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 1906 of file stm32f4xx.h.
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 1907 of file stm32f4xx.h.
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 1908 of file stm32f4xx.h.
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 1909 of file stm32f4xx.h.
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 1910 of file stm32f4xx.h.
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 1911 of file stm32f4xx.h.
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 1894 of file stm32f4xx.h.
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 1912 of file stm32f4xx.h.
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 1913 of file stm32f4xx.h.
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 1914 of file stm32f4xx.h.
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 1915 of file stm32f4xx.h.
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 1916 of file stm32f4xx.h.
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 1917 of file stm32f4xx.h.
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 1918 of file stm32f4xx.h.
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 1919 of file stm32f4xx.h.
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 1920 of file stm32f4xx.h.
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 1921 of file stm32f4xx.h.
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 1895 of file stm32f4xx.h.
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 1922 of file stm32f4xx.h.
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 1923 of file stm32f4xx.h.
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 1896 of file stm32f4xx.h.
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 1897 of file stm32f4xx.h.
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 1898 of file stm32f4xx.h.
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 1899 of file stm32f4xx.h.
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 1900 of file stm32f4xx.h.
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 1901 of file stm32f4xx.h.
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2368 of file stm32f4xx.h.
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2369 of file stm32f4xx.h.
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2378 of file stm32f4xx.h.
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2379 of file stm32f4xx.h.
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2380 of file stm32f4xx.h.
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2381 of file stm32f4xx.h.
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2382 of file stm32f4xx.h.
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2383 of file stm32f4xx.h.
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2384 of file stm32f4xx.h.
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2385 of file stm32f4xx.h.
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2386 of file stm32f4xx.h.
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2387 of file stm32f4xx.h.
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2370 of file stm32f4xx.h.
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2388 of file stm32f4xx.h.
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2389 of file stm32f4xx.h.
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2390 of file stm32f4xx.h.
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2391 of file stm32f4xx.h.
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2392 of file stm32f4xx.h.
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2393 of file stm32f4xx.h.
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2394 of file stm32f4xx.h.
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2395 of file stm32f4xx.h.
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2396 of file stm32f4xx.h.
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2397 of file stm32f4xx.h.
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2371 of file stm32f4xx.h.
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2398 of file stm32f4xx.h.
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2399 of file stm32f4xx.h.
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2372 of file stm32f4xx.h.
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2373 of file stm32f4xx.h.
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2374 of file stm32f4xx.h.
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2375 of file stm32f4xx.h.
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2376 of file stm32f4xx.h.
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2377 of file stm32f4xx.h.
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2232 of file stm32f4xx.h.
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2233 of file stm32f4xx.h.
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2242 of file stm32f4xx.h.
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2243 of file stm32f4xx.h.
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2244 of file stm32f4xx.h.
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2245 of file stm32f4xx.h.
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2246 of file stm32f4xx.h.
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2247 of file stm32f4xx.h.
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2248 of file stm32f4xx.h.
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2249 of file stm32f4xx.h.
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2250 of file stm32f4xx.h.
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2251 of file stm32f4xx.h.
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2234 of file stm32f4xx.h.
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2252 of file stm32f4xx.h.
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2253 of file stm32f4xx.h.
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2254 of file stm32f4xx.h.
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2255 of file stm32f4xx.h.
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2256 of file stm32f4xx.h.
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2257 of file stm32f4xx.h.
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2258 of file stm32f4xx.h.
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2259 of file stm32f4xx.h.
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2260 of file stm32f4xx.h.
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2261 of file stm32f4xx.h.
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2235 of file stm32f4xx.h.
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2262 of file stm32f4xx.h.
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2263 of file stm32f4xx.h.
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2236 of file stm32f4xx.h.
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2237 of file stm32f4xx.h.
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2238 of file stm32f4xx.h.
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2239 of file stm32f4xx.h.
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2240 of file stm32f4xx.h.
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2241 of file stm32f4xx.h.
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2708 of file stm32f4xx.h.
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2709 of file stm32f4xx.h.
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2718 of file stm32f4xx.h.
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2719 of file stm32f4xx.h.
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2720 of file stm32f4xx.h.
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2721 of file stm32f4xx.h.
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2722 of file stm32f4xx.h.
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2723 of file stm32f4xx.h.
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2724 of file stm32f4xx.h.
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2725 of file stm32f4xx.h.
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2726 of file stm32f4xx.h.
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2727 of file stm32f4xx.h.
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2710 of file stm32f4xx.h.
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2728 of file stm32f4xx.h.
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2729 of file stm32f4xx.h.
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2730 of file stm32f4xx.h.
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2731 of file stm32f4xx.h.
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2732 of file stm32f4xx.h.
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2733 of file stm32f4xx.h.
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2734 of file stm32f4xx.h.
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2735 of file stm32f4xx.h.
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2736 of file stm32f4xx.h.
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2737 of file stm32f4xx.h.
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2711 of file stm32f4xx.h.
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2738 of file stm32f4xx.h.
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2739 of file stm32f4xx.h.
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2712 of file stm32f4xx.h.
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2713 of file stm32f4xx.h.
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2714 of file stm32f4xx.h.
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2715 of file stm32f4xx.h.
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2716 of file stm32f4xx.h.
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2717 of file stm32f4xx.h.
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2266 of file stm32f4xx.h.
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2267 of file stm32f4xx.h.
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2276 of file stm32f4xx.h.
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2277 of file stm32f4xx.h.
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2278 of file stm32f4xx.h.
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2279 of file stm32f4xx.h.
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2280 of file stm32f4xx.h.
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2281 of file stm32f4xx.h.
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2282 of file stm32f4xx.h.
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2283 of file stm32f4xx.h.
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2284 of file stm32f4xx.h.
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2285 of file stm32f4xx.h.
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2268 of file stm32f4xx.h.
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2286 of file stm32f4xx.h.
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2287 of file stm32f4xx.h.
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2288 of file stm32f4xx.h.
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2289 of file stm32f4xx.h.
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2290 of file stm32f4xx.h.
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2291 of file stm32f4xx.h.
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2292 of file stm32f4xx.h.
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2293 of file stm32f4xx.h.
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2294 of file stm32f4xx.h.
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2295 of file stm32f4xx.h.
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2269 of file stm32f4xx.h.
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2296 of file stm32f4xx.h.
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2297 of file stm32f4xx.h.
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2270 of file stm32f4xx.h.
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2271 of file stm32f4xx.h.
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2272 of file stm32f4xx.h.
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2273 of file stm32f4xx.h.
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2274 of file stm32f4xx.h.
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2275 of file stm32f4xx.h.
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2742 of file stm32f4xx.h.
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2743 of file stm32f4xx.h.
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2752 of file stm32f4xx.h.
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2753 of file stm32f4xx.h.
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2754 of file stm32f4xx.h.
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2755 of file stm32f4xx.h.
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2756 of file stm32f4xx.h.
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2757 of file stm32f4xx.h.
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2758 of file stm32f4xx.h.
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2759 of file stm32f4xx.h.
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2760 of file stm32f4xx.h.
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2761 of file stm32f4xx.h.
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2744 of file stm32f4xx.h.
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2762 of file stm32f4xx.h.
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2763 of file stm32f4xx.h.
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2764 of file stm32f4xx.h.
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2765 of file stm32f4xx.h.
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2766 of file stm32f4xx.h.
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2767 of file stm32f4xx.h.
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2768 of file stm32f4xx.h.
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2769 of file stm32f4xx.h.
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2770 of file stm32f4xx.h.
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2771 of file stm32f4xx.h.
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2745 of file stm32f4xx.h.
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2772 of file stm32f4xx.h.
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2773 of file stm32f4xx.h.
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2746 of file stm32f4xx.h.
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2747 of file stm32f4xx.h.
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2748 of file stm32f4xx.h.
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2749 of file stm32f4xx.h.
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2750 of file stm32f4xx.h.
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2751 of file stm32f4xx.h.
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2300 of file stm32f4xx.h.
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2301 of file stm32f4xx.h.
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2310 of file stm32f4xx.h.
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2311 of file stm32f4xx.h.
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2312 of file stm32f4xx.h.
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2313 of file stm32f4xx.h.
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2314 of file stm32f4xx.h.
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2315 of file stm32f4xx.h.
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2316 of file stm32f4xx.h.
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2317 of file stm32f4xx.h.
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2318 of file stm32f4xx.h.
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2319 of file stm32f4xx.h.
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2302 of file stm32f4xx.h.
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2320 of file stm32f4xx.h.
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2321 of file stm32f4xx.h.
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2322 of file stm32f4xx.h.
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2323 of file stm32f4xx.h.
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2324 of file stm32f4xx.h.
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2325 of file stm32f4xx.h.
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2326 of file stm32f4xx.h.
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2327 of file stm32f4xx.h.
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2328 of file stm32f4xx.h.
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2329 of file stm32f4xx.h.
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2303 of file stm32f4xx.h.
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2330 of file stm32f4xx.h.
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2331 of file stm32f4xx.h.
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2304 of file stm32f4xx.h.
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2305 of file stm32f4xx.h.
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2306 of file stm32f4xx.h.
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2307 of file stm32f4xx.h.
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2308 of file stm32f4xx.h.
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2309 of file stm32f4xx.h.
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2776 of file stm32f4xx.h.
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2777 of file stm32f4xx.h.
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2786 of file stm32f4xx.h.
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2787 of file stm32f4xx.h.
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2788 of file stm32f4xx.h.
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2789 of file stm32f4xx.h.
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2790 of file stm32f4xx.h.
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2791 of file stm32f4xx.h.
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2792 of file stm32f4xx.h.
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2793 of file stm32f4xx.h.
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2794 of file stm32f4xx.h.
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2795 of file stm32f4xx.h.
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2778 of file stm32f4xx.h.
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2796 of file stm32f4xx.h.
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2797 of file stm32f4xx.h.
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2798 of file stm32f4xx.h.
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2799 of file stm32f4xx.h.
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2800 of file stm32f4xx.h.
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2801 of file stm32f4xx.h.
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2802 of file stm32f4xx.h.
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2803 of file stm32f4xx.h.
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2804 of file stm32f4xx.h.
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2805 of file stm32f4xx.h.
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2779 of file stm32f4xx.h.
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2806 of file stm32f4xx.h.
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2807 of file stm32f4xx.h.
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2780 of file stm32f4xx.h.
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2781 of file stm32f4xx.h.
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2782 of file stm32f4xx.h.
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2783 of file stm32f4xx.h.
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2784 of file stm32f4xx.h.
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2785 of file stm32f4xx.h.
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2334 of file stm32f4xx.h.
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2335 of file stm32f4xx.h.
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2344 of file stm32f4xx.h.
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2345 of file stm32f4xx.h.
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2346 of file stm32f4xx.h.
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2347 of file stm32f4xx.h.
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2348 of file stm32f4xx.h.
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2349 of file stm32f4xx.h.
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2350 of file stm32f4xx.h.
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2351 of file stm32f4xx.h.
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2352 of file stm32f4xx.h.
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2353 of file stm32f4xx.h.
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2336 of file stm32f4xx.h.
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2354 of file stm32f4xx.h.
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2355 of file stm32f4xx.h.
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2356 of file stm32f4xx.h.
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2357 of file stm32f4xx.h.
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2358 of file stm32f4xx.h.
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2359 of file stm32f4xx.h.
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2360 of file stm32f4xx.h.
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2361 of file stm32f4xx.h.
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2362 of file stm32f4xx.h.
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2363 of file stm32f4xx.h.
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2337 of file stm32f4xx.h.
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2364 of file stm32f4xx.h.
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2365 of file stm32f4xx.h.
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2338 of file stm32f4xx.h.
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2339 of file stm32f4xx.h.
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2340 of file stm32f4xx.h.
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2341 of file stm32f4xx.h.
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2342 of file stm32f4xx.h.
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2343 of file stm32f4xx.h.
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2810 of file stm32f4xx.h.
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2811 of file stm32f4xx.h.
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2820 of file stm32f4xx.h.
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2821 of file stm32f4xx.h.
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2822 of file stm32f4xx.h.
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2823 of file stm32f4xx.h.
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2824 of file stm32f4xx.h.
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2825 of file stm32f4xx.h.
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2826 of file stm32f4xx.h.
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2827 of file stm32f4xx.h.
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2828 of file stm32f4xx.h.
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2829 of file stm32f4xx.h.
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2812 of file stm32f4xx.h.
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2830 of file stm32f4xx.h.
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2831 of file stm32f4xx.h.
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2832 of file stm32f4xx.h.
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2833 of file stm32f4xx.h.
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2834 of file stm32f4xx.h.
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2835 of file stm32f4xx.h.
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2836 of file stm32f4xx.h.
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2837 of file stm32f4xx.h.
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2838 of file stm32f4xx.h.
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2839 of file stm32f4xx.h.
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2813 of file stm32f4xx.h.
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2840 of file stm32f4xx.h.
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2841 of file stm32f4xx.h.
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2814 of file stm32f4xx.h.
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2815 of file stm32f4xx.h.
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2816 of file stm32f4xx.h.
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2817 of file stm32f4xx.h.
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2818 of file stm32f4xx.h.
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2819 of file stm32f4xx.h.
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 1926 of file stm32f4xx.h.
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 1927 of file stm32f4xx.h.
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 1936 of file stm32f4xx.h.
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 1937 of file stm32f4xx.h.
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 1938 of file stm32f4xx.h.
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 1939 of file stm32f4xx.h.
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 1940 of file stm32f4xx.h.
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 1941 of file stm32f4xx.h.
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 1942 of file stm32f4xx.h.
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 1943 of file stm32f4xx.h.
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 1944 of file stm32f4xx.h.
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 1945 of file stm32f4xx.h.
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 1928 of file stm32f4xx.h.
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 1946 of file stm32f4xx.h.
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 1947 of file stm32f4xx.h.
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 1948 of file stm32f4xx.h.
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 1949 of file stm32f4xx.h.
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 1950 of file stm32f4xx.h.
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 1951 of file stm32f4xx.h.
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 1952 of file stm32f4xx.h.
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 1953 of file stm32f4xx.h.
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 1954 of file stm32f4xx.h.
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 1955 of file stm32f4xx.h.
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 1929 of file stm32f4xx.h.
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 1956 of file stm32f4xx.h.
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 1957 of file stm32f4xx.h.
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 1930 of file stm32f4xx.h.
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 1931 of file stm32f4xx.h.
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 1932 of file stm32f4xx.h.
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 1933 of file stm32f4xx.h.
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 1934 of file stm32f4xx.h.
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 1935 of file stm32f4xx.h.
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2402 of file stm32f4xx.h.
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2403 of file stm32f4xx.h.
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2412 of file stm32f4xx.h.
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2413 of file stm32f4xx.h.
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2414 of file stm32f4xx.h.
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2415 of file stm32f4xx.h.
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2416 of file stm32f4xx.h.
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2417 of file stm32f4xx.h.
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2418 of file stm32f4xx.h.
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2419 of file stm32f4xx.h.
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2420 of file stm32f4xx.h.
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2421 of file stm32f4xx.h.
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2404 of file stm32f4xx.h.
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2422 of file stm32f4xx.h.
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2423 of file stm32f4xx.h.
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2424 of file stm32f4xx.h.
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2425 of file stm32f4xx.h.
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2426 of file stm32f4xx.h.
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2427 of file stm32f4xx.h.
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2428 of file stm32f4xx.h.
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2429 of file stm32f4xx.h.
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2430 of file stm32f4xx.h.
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2431 of file stm32f4xx.h.
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2405 of file stm32f4xx.h.
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2432 of file stm32f4xx.h.
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2433 of file stm32f4xx.h.
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2406 of file stm32f4xx.h.
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2407 of file stm32f4xx.h.
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2408 of file stm32f4xx.h.
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2409 of file stm32f4xx.h.
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2410 of file stm32f4xx.h.
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2411 of file stm32f4xx.h.
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 1960 of file stm32f4xx.h.
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 1961 of file stm32f4xx.h.
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 1970 of file stm32f4xx.h.
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 1971 of file stm32f4xx.h.
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 1972 of file stm32f4xx.h.
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 1973 of file stm32f4xx.h.
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 1974 of file stm32f4xx.h.
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 1975 of file stm32f4xx.h.
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 1976 of file stm32f4xx.h.
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 1977 of file stm32f4xx.h.
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 1978 of file stm32f4xx.h.
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 1979 of file stm32f4xx.h.
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 1962 of file stm32f4xx.h.
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 1980 of file stm32f4xx.h.
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 1981 of file stm32f4xx.h.
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 1982 of file stm32f4xx.h.
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 1983 of file stm32f4xx.h.
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 1984 of file stm32f4xx.h.
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 1985 of file stm32f4xx.h.
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 1986 of file stm32f4xx.h.
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 1987 of file stm32f4xx.h.
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 1988 of file stm32f4xx.h.
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 1989 of file stm32f4xx.h.
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 1963 of file stm32f4xx.h.
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 1990 of file stm32f4xx.h.
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 1991 of file stm32f4xx.h.
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 1964 of file stm32f4xx.h.
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 1965 of file stm32f4xx.h.
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 1966 of file stm32f4xx.h.
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 1967 of file stm32f4xx.h.
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 1968 of file stm32f4xx.h.
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 1969 of file stm32f4xx.h.
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2436 of file stm32f4xx.h.
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2437 of file stm32f4xx.h.
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2446 of file stm32f4xx.h.
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2447 of file stm32f4xx.h.
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2448 of file stm32f4xx.h.
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2449 of file stm32f4xx.h.
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2450 of file stm32f4xx.h.
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2451 of file stm32f4xx.h.
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2452 of file stm32f4xx.h.
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2453 of file stm32f4xx.h.
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2454 of file stm32f4xx.h.
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2455 of file stm32f4xx.h.
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2438 of file stm32f4xx.h.
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2456 of file stm32f4xx.h.
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2457 of file stm32f4xx.h.
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2458 of file stm32f4xx.h.
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2459 of file stm32f4xx.h.
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2460 of file stm32f4xx.h.
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2461 of file stm32f4xx.h.
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2462 of file stm32f4xx.h.
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2463 of file stm32f4xx.h.
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2464 of file stm32f4xx.h.
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2465 of file stm32f4xx.h.
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2439 of file stm32f4xx.h.
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2466 of file stm32f4xx.h.
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2467 of file stm32f4xx.h.
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2440 of file stm32f4xx.h.
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2441 of file stm32f4xx.h.
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2442 of file stm32f4xx.h.
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2443 of file stm32f4xx.h.
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2444 of file stm32f4xx.h.
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2445 of file stm32f4xx.h.
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 1994 of file stm32f4xx.h.
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 1995 of file stm32f4xx.h.
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2004 of file stm32f4xx.h.
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2005 of file stm32f4xx.h.
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2006 of file stm32f4xx.h.
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2007 of file stm32f4xx.h.
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2008 of file stm32f4xx.h.
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2009 of file stm32f4xx.h.
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2010 of file stm32f4xx.h.
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2011 of file stm32f4xx.h.
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2012 of file stm32f4xx.h.
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2013 of file stm32f4xx.h.
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 1996 of file stm32f4xx.h.
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2014 of file stm32f4xx.h.
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2015 of file stm32f4xx.h.
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2016 of file stm32f4xx.h.
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2017 of file stm32f4xx.h.
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2018 of file stm32f4xx.h.
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2019 of file stm32f4xx.h.
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2020 of file stm32f4xx.h.
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2021 of file stm32f4xx.h.
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2022 of file stm32f4xx.h.
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2023 of file stm32f4xx.h.
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 1997 of file stm32f4xx.h.
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2024 of file stm32f4xx.h.
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2025 of file stm32f4xx.h.
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 1998 of file stm32f4xx.h.
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 1999 of file stm32f4xx.h.
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2000 of file stm32f4xx.h.
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2001 of file stm32f4xx.h.
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2002 of file stm32f4xx.h.
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2003 of file stm32f4xx.h.
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2470 of file stm32f4xx.h.
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2471 of file stm32f4xx.h.
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2480 of file stm32f4xx.h.
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2481 of file stm32f4xx.h.
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2482 of file stm32f4xx.h.
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2483 of file stm32f4xx.h.
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2484 of file stm32f4xx.h.
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2485 of file stm32f4xx.h.
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2486 of file stm32f4xx.h.
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2487 of file stm32f4xx.h.
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2488 of file stm32f4xx.h.
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2489 of file stm32f4xx.h.
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2472 of file stm32f4xx.h.
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2490 of file stm32f4xx.h.
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2491 of file stm32f4xx.h.
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2492 of file stm32f4xx.h.
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2493 of file stm32f4xx.h.
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2494 of file stm32f4xx.h.
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2495 of file stm32f4xx.h.
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2496 of file stm32f4xx.h.
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2497 of file stm32f4xx.h.
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2498 of file stm32f4xx.h.
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2499 of file stm32f4xx.h.
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2473 of file stm32f4xx.h.
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2500 of file stm32f4xx.h.
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2501 of file stm32f4xx.h.
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2474 of file stm32f4xx.h.
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2475 of file stm32f4xx.h.
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2476 of file stm32f4xx.h.
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2477 of file stm32f4xx.h.
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2478 of file stm32f4xx.h.
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2479 of file stm32f4xx.h.
| #define CAN_F4R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2028 of file stm32f4xx.h.
| #define CAN_F4R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2029 of file stm32f4xx.h.
| #define CAN_F4R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2038 of file stm32f4xx.h.
| #define CAN_F4R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2039 of file stm32f4xx.h.
| #define CAN_F4R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2040 of file stm32f4xx.h.
| #define CAN_F4R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2041 of file stm32f4xx.h.
| #define CAN_F4R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2042 of file stm32f4xx.h.
| #define CAN_F4R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2043 of file stm32f4xx.h.
| #define CAN_F4R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2044 of file stm32f4xx.h.
| #define CAN_F4R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2045 of file stm32f4xx.h.
| #define CAN_F4R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2046 of file stm32f4xx.h.
| #define CAN_F4R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2047 of file stm32f4xx.h.
| #define CAN_F4R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2030 of file stm32f4xx.h.
| #define CAN_F4R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2048 of file stm32f4xx.h.
| #define CAN_F4R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2049 of file stm32f4xx.h.
| #define CAN_F4R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2050 of file stm32f4xx.h.
| #define CAN_F4R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2051 of file stm32f4xx.h.
| #define CAN_F4R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2052 of file stm32f4xx.h.
| #define CAN_F4R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2053 of file stm32f4xx.h.
| #define CAN_F4R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2054 of file stm32f4xx.h.
| #define CAN_F4R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2055 of file stm32f4xx.h.
| #define CAN_F4R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2056 of file stm32f4xx.h.
| #define CAN_F4R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2057 of file stm32f4xx.h.
| #define CAN_F4R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2031 of file stm32f4xx.h.
| #define CAN_F4R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2058 of file stm32f4xx.h.
| #define CAN_F4R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2059 of file stm32f4xx.h.
| #define CAN_F4R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2032 of file stm32f4xx.h.
| #define CAN_F4R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2033 of file stm32f4xx.h.
| #define CAN_F4R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2034 of file stm32f4xx.h.
| #define CAN_F4R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2035 of file stm32f4xx.h.
| #define CAN_F4R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2036 of file stm32f4xx.h.
| #define CAN_F4R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2037 of file stm32f4xx.h.
| #define CAN_F4R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2504 of file stm32f4xx.h.
| #define CAN_F4R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2505 of file stm32f4xx.h.
| #define CAN_F4R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2514 of file stm32f4xx.h.
| #define CAN_F4R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2515 of file stm32f4xx.h.
| #define CAN_F4R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2516 of file stm32f4xx.h.
| #define CAN_F4R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2517 of file stm32f4xx.h.
| #define CAN_F4R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2518 of file stm32f4xx.h.
| #define CAN_F4R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2519 of file stm32f4xx.h.
| #define CAN_F4R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2520 of file stm32f4xx.h.
| #define CAN_F4R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2521 of file stm32f4xx.h.
| #define CAN_F4R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2522 of file stm32f4xx.h.
| #define CAN_F4R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2523 of file stm32f4xx.h.
| #define CAN_F4R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2506 of file stm32f4xx.h.
| #define CAN_F4R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2524 of file stm32f4xx.h.
| #define CAN_F4R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2525 of file stm32f4xx.h.
| #define CAN_F4R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2526 of file stm32f4xx.h.
| #define CAN_F4R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2527 of file stm32f4xx.h.
| #define CAN_F4R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2528 of file stm32f4xx.h.
| #define CAN_F4R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2529 of file stm32f4xx.h.
| #define CAN_F4R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2530 of file stm32f4xx.h.
| #define CAN_F4R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2531 of file stm32f4xx.h.
| #define CAN_F4R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2532 of file stm32f4xx.h.
| #define CAN_F4R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2533 of file stm32f4xx.h.
| #define CAN_F4R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2507 of file stm32f4xx.h.
| #define CAN_F4R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2534 of file stm32f4xx.h.
| #define CAN_F4R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2535 of file stm32f4xx.h.
| #define CAN_F4R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2508 of file stm32f4xx.h.
| #define CAN_F4R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2509 of file stm32f4xx.h.
| #define CAN_F4R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2510 of file stm32f4xx.h.
| #define CAN_F4R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2511 of file stm32f4xx.h.
| #define CAN_F4R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2512 of file stm32f4xx.h.
| #define CAN_F4R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2513 of file stm32f4xx.h.
| #define CAN_F5R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2062 of file stm32f4xx.h.
| #define CAN_F5R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2063 of file stm32f4xx.h.
| #define CAN_F5R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2072 of file stm32f4xx.h.
| #define CAN_F5R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2073 of file stm32f4xx.h.
| #define CAN_F5R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2074 of file stm32f4xx.h.
| #define CAN_F5R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2075 of file stm32f4xx.h.
| #define CAN_F5R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2076 of file stm32f4xx.h.
| #define CAN_F5R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2077 of file stm32f4xx.h.
| #define CAN_F5R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2078 of file stm32f4xx.h.
| #define CAN_F5R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2079 of file stm32f4xx.h.
| #define CAN_F5R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2080 of file stm32f4xx.h.
| #define CAN_F5R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2081 of file stm32f4xx.h.
| #define CAN_F5R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2064 of file stm32f4xx.h.
| #define CAN_F5R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2082 of file stm32f4xx.h.
| #define CAN_F5R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2083 of file stm32f4xx.h.
| #define CAN_F5R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2084 of file stm32f4xx.h.
| #define CAN_F5R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2085 of file stm32f4xx.h.
| #define CAN_F5R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2086 of file stm32f4xx.h.
| #define CAN_F5R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2087 of file stm32f4xx.h.
| #define CAN_F5R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2088 of file stm32f4xx.h.
| #define CAN_F5R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2089 of file stm32f4xx.h.
| #define CAN_F5R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2090 of file stm32f4xx.h.
| #define CAN_F5R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2091 of file stm32f4xx.h.
| #define CAN_F5R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2065 of file stm32f4xx.h.
| #define CAN_F5R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2092 of file stm32f4xx.h.
| #define CAN_F5R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2093 of file stm32f4xx.h.
| #define CAN_F5R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2066 of file stm32f4xx.h.
| #define CAN_F5R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2067 of file stm32f4xx.h.
| #define CAN_F5R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2068 of file stm32f4xx.h.
| #define CAN_F5R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2069 of file stm32f4xx.h.
| #define CAN_F5R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2070 of file stm32f4xx.h.
| #define CAN_F5R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2071 of file stm32f4xx.h.
| #define CAN_F5R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2538 of file stm32f4xx.h.
| #define CAN_F5R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2539 of file stm32f4xx.h.
| #define CAN_F5R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2548 of file stm32f4xx.h.
| #define CAN_F5R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2549 of file stm32f4xx.h.
| #define CAN_F5R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2550 of file stm32f4xx.h.
| #define CAN_F5R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2551 of file stm32f4xx.h.
| #define CAN_F5R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2552 of file stm32f4xx.h.
| #define CAN_F5R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2553 of file stm32f4xx.h.
| #define CAN_F5R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2554 of file stm32f4xx.h.
| #define CAN_F5R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2555 of file stm32f4xx.h.
| #define CAN_F5R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2556 of file stm32f4xx.h.
| #define CAN_F5R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2557 of file stm32f4xx.h.
| #define CAN_F5R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2540 of file stm32f4xx.h.
| #define CAN_F5R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2558 of file stm32f4xx.h.
| #define CAN_F5R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2559 of file stm32f4xx.h.
| #define CAN_F5R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2560 of file stm32f4xx.h.
| #define CAN_F5R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2561 of file stm32f4xx.h.
| #define CAN_F5R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2562 of file stm32f4xx.h.
| #define CAN_F5R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2563 of file stm32f4xx.h.
| #define CAN_F5R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2564 of file stm32f4xx.h.
| #define CAN_F5R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2565 of file stm32f4xx.h.
| #define CAN_F5R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2566 of file stm32f4xx.h.
| #define CAN_F5R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2567 of file stm32f4xx.h.
| #define CAN_F5R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2541 of file stm32f4xx.h.
| #define CAN_F5R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2568 of file stm32f4xx.h.
| #define CAN_F5R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2569 of file stm32f4xx.h.
| #define CAN_F5R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2542 of file stm32f4xx.h.
| #define CAN_F5R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2543 of file stm32f4xx.h.
| #define CAN_F5R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2544 of file stm32f4xx.h.
| #define CAN_F5R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2545 of file stm32f4xx.h.
| #define CAN_F5R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2546 of file stm32f4xx.h.
| #define CAN_F5R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2547 of file stm32f4xx.h.
| #define CAN_F6R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2096 of file stm32f4xx.h.
| #define CAN_F6R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2097 of file stm32f4xx.h.
| #define CAN_F6R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2106 of file stm32f4xx.h.
| #define CAN_F6R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2107 of file stm32f4xx.h.
| #define CAN_F6R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2108 of file stm32f4xx.h.
| #define CAN_F6R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2109 of file stm32f4xx.h.
| #define CAN_F6R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2110 of file stm32f4xx.h.
| #define CAN_F6R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2111 of file stm32f4xx.h.
| #define CAN_F6R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2112 of file stm32f4xx.h.
| #define CAN_F6R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2113 of file stm32f4xx.h.
| #define CAN_F6R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2114 of file stm32f4xx.h.
| #define CAN_F6R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2115 of file stm32f4xx.h.
| #define CAN_F6R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2098 of file stm32f4xx.h.
| #define CAN_F6R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2116 of file stm32f4xx.h.
| #define CAN_F6R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2117 of file stm32f4xx.h.
| #define CAN_F6R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2118 of file stm32f4xx.h.
| #define CAN_F6R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2119 of file stm32f4xx.h.
| #define CAN_F6R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2120 of file stm32f4xx.h.
| #define CAN_F6R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2121 of file stm32f4xx.h.
| #define CAN_F6R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2122 of file stm32f4xx.h.
| #define CAN_F6R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2123 of file stm32f4xx.h.
| #define CAN_F6R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2124 of file stm32f4xx.h.
| #define CAN_F6R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2125 of file stm32f4xx.h.
| #define CAN_F6R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2099 of file stm32f4xx.h.
| #define CAN_F6R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2126 of file stm32f4xx.h.
| #define CAN_F6R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2127 of file stm32f4xx.h.
| #define CAN_F6R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2100 of file stm32f4xx.h.
| #define CAN_F6R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2101 of file stm32f4xx.h.
| #define CAN_F6R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2102 of file stm32f4xx.h.
| #define CAN_F6R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2103 of file stm32f4xx.h.
| #define CAN_F6R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2104 of file stm32f4xx.h.
| #define CAN_F6R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2105 of file stm32f4xx.h.
| #define CAN_F6R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2572 of file stm32f4xx.h.
| #define CAN_F6R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2573 of file stm32f4xx.h.
| #define CAN_F6R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2582 of file stm32f4xx.h.
| #define CAN_F6R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2583 of file stm32f4xx.h.
| #define CAN_F6R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2584 of file stm32f4xx.h.
| #define CAN_F6R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2585 of file stm32f4xx.h.
| #define CAN_F6R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2586 of file stm32f4xx.h.
| #define CAN_F6R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2587 of file stm32f4xx.h.
| #define CAN_F6R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2588 of file stm32f4xx.h.
| #define CAN_F6R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2589 of file stm32f4xx.h.
| #define CAN_F6R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2590 of file stm32f4xx.h.
| #define CAN_F6R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2591 of file stm32f4xx.h.
| #define CAN_F6R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2574 of file stm32f4xx.h.
| #define CAN_F6R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2592 of file stm32f4xx.h.
| #define CAN_F6R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2593 of file stm32f4xx.h.
| #define CAN_F6R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2594 of file stm32f4xx.h.
| #define CAN_F6R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2595 of file stm32f4xx.h.
| #define CAN_F6R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2596 of file stm32f4xx.h.
| #define CAN_F6R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2597 of file stm32f4xx.h.
| #define CAN_F6R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2598 of file stm32f4xx.h.
| #define CAN_F6R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2599 of file stm32f4xx.h.
| #define CAN_F6R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2600 of file stm32f4xx.h.
| #define CAN_F6R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2601 of file stm32f4xx.h.
| #define CAN_F6R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2575 of file stm32f4xx.h.
| #define CAN_F6R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2602 of file stm32f4xx.h.
| #define CAN_F6R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2603 of file stm32f4xx.h.
| #define CAN_F6R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2576 of file stm32f4xx.h.
| #define CAN_F6R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2577 of file stm32f4xx.h.
| #define CAN_F6R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2578 of file stm32f4xx.h.
| #define CAN_F6R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2579 of file stm32f4xx.h.
| #define CAN_F6R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2580 of file stm32f4xx.h.
| #define CAN_F6R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2581 of file stm32f4xx.h.
| #define CAN_F7R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2130 of file stm32f4xx.h.
| #define CAN_F7R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2131 of file stm32f4xx.h.
| #define CAN_F7R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2140 of file stm32f4xx.h.
| #define CAN_F7R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2141 of file stm32f4xx.h.
| #define CAN_F7R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2142 of file stm32f4xx.h.
| #define CAN_F7R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2143 of file stm32f4xx.h.
| #define CAN_F7R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2144 of file stm32f4xx.h.
| #define CAN_F7R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2145 of file stm32f4xx.h.
| #define CAN_F7R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2146 of file stm32f4xx.h.
| #define CAN_F7R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2147 of file stm32f4xx.h.
| #define CAN_F7R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2148 of file stm32f4xx.h.
| #define CAN_F7R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2149 of file stm32f4xx.h.
| #define CAN_F7R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2132 of file stm32f4xx.h.
| #define CAN_F7R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2150 of file stm32f4xx.h.
| #define CAN_F7R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2151 of file stm32f4xx.h.
| #define CAN_F7R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2152 of file stm32f4xx.h.
| #define CAN_F7R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2153 of file stm32f4xx.h.
| #define CAN_F7R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2154 of file stm32f4xx.h.
| #define CAN_F7R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2155 of file stm32f4xx.h.
| #define CAN_F7R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2156 of file stm32f4xx.h.
| #define CAN_F7R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2157 of file stm32f4xx.h.
| #define CAN_F7R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2158 of file stm32f4xx.h.
| #define CAN_F7R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2159 of file stm32f4xx.h.
| #define CAN_F7R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2133 of file stm32f4xx.h.
| #define CAN_F7R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2160 of file stm32f4xx.h.
| #define CAN_F7R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2161 of file stm32f4xx.h.
| #define CAN_F7R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2134 of file stm32f4xx.h.
| #define CAN_F7R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2135 of file stm32f4xx.h.
| #define CAN_F7R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2136 of file stm32f4xx.h.
| #define CAN_F7R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2137 of file stm32f4xx.h.
| #define CAN_F7R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2138 of file stm32f4xx.h.
| #define CAN_F7R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2139 of file stm32f4xx.h.
| #define CAN_F7R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2606 of file stm32f4xx.h.
| #define CAN_F7R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2607 of file stm32f4xx.h.
| #define CAN_F7R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2616 of file stm32f4xx.h.
| #define CAN_F7R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2617 of file stm32f4xx.h.
| #define CAN_F7R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2618 of file stm32f4xx.h.
| #define CAN_F7R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2619 of file stm32f4xx.h.
| #define CAN_F7R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2620 of file stm32f4xx.h.
| #define CAN_F7R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2621 of file stm32f4xx.h.
| #define CAN_F7R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2622 of file stm32f4xx.h.
| #define CAN_F7R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2623 of file stm32f4xx.h.
| #define CAN_F7R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2624 of file stm32f4xx.h.
| #define CAN_F7R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2625 of file stm32f4xx.h.
| #define CAN_F7R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2608 of file stm32f4xx.h.
| #define CAN_F7R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2626 of file stm32f4xx.h.
| #define CAN_F7R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2627 of file stm32f4xx.h.
| #define CAN_F7R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2628 of file stm32f4xx.h.
| #define CAN_F7R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2629 of file stm32f4xx.h.
| #define CAN_F7R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2630 of file stm32f4xx.h.
| #define CAN_F7R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2631 of file stm32f4xx.h.
| #define CAN_F7R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2632 of file stm32f4xx.h.
| #define CAN_F7R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2633 of file stm32f4xx.h.
| #define CAN_F7R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2634 of file stm32f4xx.h.
| #define CAN_F7R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2635 of file stm32f4xx.h.
| #define CAN_F7R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2609 of file stm32f4xx.h.
| #define CAN_F7R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2636 of file stm32f4xx.h.
| #define CAN_F7R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2637 of file stm32f4xx.h.
| #define CAN_F7R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2610 of file stm32f4xx.h.
| #define CAN_F7R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2611 of file stm32f4xx.h.
| #define CAN_F7R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2612 of file stm32f4xx.h.
| #define CAN_F7R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2613 of file stm32f4xx.h.
| #define CAN_F7R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2614 of file stm32f4xx.h.
| #define CAN_F7R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2615 of file stm32f4xx.h.
| #define CAN_F8R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2164 of file stm32f4xx.h.
| #define CAN_F8R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2165 of file stm32f4xx.h.
| #define CAN_F8R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2174 of file stm32f4xx.h.
| #define CAN_F8R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2175 of file stm32f4xx.h.
| #define CAN_F8R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2176 of file stm32f4xx.h.
| #define CAN_F8R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2177 of file stm32f4xx.h.
| #define CAN_F8R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2178 of file stm32f4xx.h.
| #define CAN_F8R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2179 of file stm32f4xx.h.
| #define CAN_F8R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2180 of file stm32f4xx.h.
| #define CAN_F8R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2181 of file stm32f4xx.h.
| #define CAN_F8R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2182 of file stm32f4xx.h.
| #define CAN_F8R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2183 of file stm32f4xx.h.
| #define CAN_F8R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2166 of file stm32f4xx.h.
| #define CAN_F8R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2184 of file stm32f4xx.h.
| #define CAN_F8R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2185 of file stm32f4xx.h.
| #define CAN_F8R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2186 of file stm32f4xx.h.
| #define CAN_F8R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2187 of file stm32f4xx.h.
| #define CAN_F8R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2188 of file stm32f4xx.h.
| #define CAN_F8R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2189 of file stm32f4xx.h.
| #define CAN_F8R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2190 of file stm32f4xx.h.
| #define CAN_F8R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2191 of file stm32f4xx.h.
| #define CAN_F8R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2192 of file stm32f4xx.h.
| #define CAN_F8R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2193 of file stm32f4xx.h.
| #define CAN_F8R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2167 of file stm32f4xx.h.
| #define CAN_F8R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2194 of file stm32f4xx.h.
| #define CAN_F8R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2195 of file stm32f4xx.h.
| #define CAN_F8R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2168 of file stm32f4xx.h.
| #define CAN_F8R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2169 of file stm32f4xx.h.
| #define CAN_F8R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2170 of file stm32f4xx.h.
| #define CAN_F8R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2171 of file stm32f4xx.h.
| #define CAN_F8R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2172 of file stm32f4xx.h.
| #define CAN_F8R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2173 of file stm32f4xx.h.
| #define CAN_F8R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2640 of file stm32f4xx.h.
| #define CAN_F8R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2641 of file stm32f4xx.h.
| #define CAN_F8R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2650 of file stm32f4xx.h.
| #define CAN_F8R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2651 of file stm32f4xx.h.
| #define CAN_F8R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2652 of file stm32f4xx.h.
| #define CAN_F8R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2653 of file stm32f4xx.h.
| #define CAN_F8R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2654 of file stm32f4xx.h.
| #define CAN_F8R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2655 of file stm32f4xx.h.
| #define CAN_F8R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2656 of file stm32f4xx.h.
| #define CAN_F8R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2657 of file stm32f4xx.h.
| #define CAN_F8R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2658 of file stm32f4xx.h.
| #define CAN_F8R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2659 of file stm32f4xx.h.
| #define CAN_F8R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2642 of file stm32f4xx.h.
| #define CAN_F8R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2660 of file stm32f4xx.h.
| #define CAN_F8R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2661 of file stm32f4xx.h.
| #define CAN_F8R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2662 of file stm32f4xx.h.
| #define CAN_F8R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2663 of file stm32f4xx.h.
| #define CAN_F8R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2664 of file stm32f4xx.h.
| #define CAN_F8R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2665 of file stm32f4xx.h.
| #define CAN_F8R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2666 of file stm32f4xx.h.
| #define CAN_F8R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2667 of file stm32f4xx.h.
| #define CAN_F8R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2668 of file stm32f4xx.h.
| #define CAN_F8R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2669 of file stm32f4xx.h.
| #define CAN_F8R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2643 of file stm32f4xx.h.
| #define CAN_F8R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2670 of file stm32f4xx.h.
| #define CAN_F8R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2671 of file stm32f4xx.h.
| #define CAN_F8R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2644 of file stm32f4xx.h.
| #define CAN_F8R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2645 of file stm32f4xx.h.
| #define CAN_F8R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2646 of file stm32f4xx.h.
| #define CAN_F8R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2647 of file stm32f4xx.h.
| #define CAN_F8R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2648 of file stm32f4xx.h.
| #define CAN_F8R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2649 of file stm32f4xx.h.
| #define CAN_F9R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2198 of file stm32f4xx.h.
| #define CAN_F9R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2199 of file stm32f4xx.h.
| #define CAN_F9R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2208 of file stm32f4xx.h.
| #define CAN_F9R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2209 of file stm32f4xx.h.
| #define CAN_F9R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2210 of file stm32f4xx.h.
| #define CAN_F9R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2211 of file stm32f4xx.h.
| #define CAN_F9R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2212 of file stm32f4xx.h.
| #define CAN_F9R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2213 of file stm32f4xx.h.
| #define CAN_F9R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2214 of file stm32f4xx.h.
| #define CAN_F9R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2215 of file stm32f4xx.h.
| #define CAN_F9R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2216 of file stm32f4xx.h.
| #define CAN_F9R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2217 of file stm32f4xx.h.
| #define CAN_F9R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2200 of file stm32f4xx.h.
| #define CAN_F9R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2218 of file stm32f4xx.h.
| #define CAN_F9R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2219 of file stm32f4xx.h.
| #define CAN_F9R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2220 of file stm32f4xx.h.
| #define CAN_F9R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2221 of file stm32f4xx.h.
| #define CAN_F9R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2222 of file stm32f4xx.h.
| #define CAN_F9R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2223 of file stm32f4xx.h.
| #define CAN_F9R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2224 of file stm32f4xx.h.
| #define CAN_F9R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2225 of file stm32f4xx.h.
| #define CAN_F9R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2226 of file stm32f4xx.h.
| #define CAN_F9R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2227 of file stm32f4xx.h.
| #define CAN_F9R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2201 of file stm32f4xx.h.
| #define CAN_F9R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2228 of file stm32f4xx.h.
| #define CAN_F9R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2229 of file stm32f4xx.h.
| #define CAN_F9R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2202 of file stm32f4xx.h.
| #define CAN_F9R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2203 of file stm32f4xx.h.
| #define CAN_F9R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2204 of file stm32f4xx.h.
| #define CAN_F9R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2205 of file stm32f4xx.h.
| #define CAN_F9R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2206 of file stm32f4xx.h.
| #define CAN_F9R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2207 of file stm32f4xx.h.
| #define CAN_F9R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 2674 of file stm32f4xx.h.
| #define CAN_F9R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 2675 of file stm32f4xx.h.
| #define CAN_F9R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 2684 of file stm32f4xx.h.
| #define CAN_F9R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 2685 of file stm32f4xx.h.
| #define CAN_F9R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 2686 of file stm32f4xx.h.
| #define CAN_F9R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 2687 of file stm32f4xx.h.
| #define CAN_F9R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 2688 of file stm32f4xx.h.
| #define CAN_F9R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 2689 of file stm32f4xx.h.
| #define CAN_F9R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 2690 of file stm32f4xx.h.
| #define CAN_F9R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 2691 of file stm32f4xx.h.
| #define CAN_F9R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 2692 of file stm32f4xx.h.
| #define CAN_F9R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 2693 of file stm32f4xx.h.
| #define CAN_F9R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 2676 of file stm32f4xx.h.
| #define CAN_F9R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 2694 of file stm32f4xx.h.
| #define CAN_F9R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 2695 of file stm32f4xx.h.
| #define CAN_F9R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 2696 of file stm32f4xx.h.
| #define CAN_F9R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 2697 of file stm32f4xx.h.
| #define CAN_F9R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 2698 of file stm32f4xx.h.
| #define CAN_F9R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 2699 of file stm32f4xx.h.
| #define CAN_F9R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 2700 of file stm32f4xx.h.
| #define CAN_F9R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 2701 of file stm32f4xx.h.
| #define CAN_F9R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 2702 of file stm32f4xx.h.
| #define CAN_F9R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 2703 of file stm32f4xx.h.
| #define CAN_F9R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 2677 of file stm32f4xx.h.
| #define CAN_F9R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 2704 of file stm32f4xx.h.
| #define CAN_F9R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 2705 of file stm32f4xx.h.
| #define CAN_F9R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 2678 of file stm32f4xx.h.
| #define CAN_F9R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 2679 of file stm32f4xx.h.
| #define CAN_F9R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 2680 of file stm32f4xx.h.
| #define CAN_F9R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 2681 of file stm32f4xx.h.
| #define CAN_F9R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 2682 of file stm32f4xx.h.
| #define CAN_F9R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 2683 of file stm32f4xx.h.
| #define CAN_FA1R_FACT ((uint16_t)0x3FFF) |
Filter Active
Definition at line 1875 of file stm32f4xx.h.
| #define CAN_FA1R_FACT0 ((uint16_t)0x0001) |
Filter 0 Active
Definition at line 1876 of file stm32f4xx.h.
| #define CAN_FA1R_FACT1 ((uint16_t)0x0002) |
Filter 1 Active
Definition at line 1877 of file stm32f4xx.h.
| #define CAN_FA1R_FACT10 ((uint16_t)0x0400) |
Filter 10 Active
Definition at line 1886 of file stm32f4xx.h.
| #define CAN_FA1R_FACT11 ((uint16_t)0x0800) |
Filter 11 Active
Definition at line 1887 of file stm32f4xx.h.
| #define CAN_FA1R_FACT12 ((uint16_t)0x1000) |
Filter 12 Active
Definition at line 1888 of file stm32f4xx.h.
| #define CAN_FA1R_FACT13 ((uint16_t)0x2000) |
Filter 13 Active
Definition at line 1889 of file stm32f4xx.h.
| #define CAN_FA1R_FACT2 ((uint16_t)0x0004) |
Filter 2 Active
Definition at line 1878 of file stm32f4xx.h.
| #define CAN_FA1R_FACT3 ((uint16_t)0x0008) |
Filter 3 Active
Definition at line 1879 of file stm32f4xx.h.
| #define CAN_FA1R_FACT4 ((uint16_t)0x0010) |
Filter 4 Active
Definition at line 1880 of file stm32f4xx.h.
| #define CAN_FA1R_FACT5 ((uint16_t)0x0020) |
Filter 5 Active
Definition at line 1881 of file stm32f4xx.h.
| #define CAN_FA1R_FACT6 ((uint16_t)0x0040) |
Filter 6 Active
Definition at line 1882 of file stm32f4xx.h.
| #define CAN_FA1R_FACT7 ((uint16_t)0x0080) |
Filter 7 Active
Definition at line 1883 of file stm32f4xx.h.
| #define CAN_FA1R_FACT8 ((uint16_t)0x0100) |
Filter 8 Active
Definition at line 1884 of file stm32f4xx.h.
| #define CAN_FA1R_FACT9 ((uint16_t)0x0200) |
Filter 9 Active
Definition at line 1885 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
Filter FIFO Assignment
Definition at line 1858 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
Filter FIFO Assignment for Filter 0
Definition at line 1859 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
Filter FIFO Assignment for Filter 1
Definition at line 1860 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
Filter FIFO Assignment for Filter 10
Definition at line 1869 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
Filter FIFO Assignment for Filter 11
Definition at line 1870 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
Filter FIFO Assignment for Filter 12
Definition at line 1871 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
Filter FIFO Assignment for Filter 13
Definition at line 1872 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
Filter FIFO Assignment for Filter 2
Definition at line 1861 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
Filter FIFO Assignment for Filter 3
Definition at line 1862 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
Filter FIFO Assignment for Filter 4
Definition at line 1863 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
Filter FIFO Assignment for Filter 5
Definition at line 1864 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
Filter FIFO Assignment for Filter 6
Definition at line 1865 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
Filter FIFO Assignment for Filter 7
Definition at line 1866 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
Filter FIFO Assignment for Filter 8
Definition at line 1867 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
Filter FIFO Assignment for Filter 9
Definition at line 1868 of file stm32f4xx.h.
| #define CAN_FM1R_FBM ((uint16_t)0x3FFF) |
Filter Mode
Definition at line 1824 of file stm32f4xx.h.
| #define CAN_FM1R_FBM0 ((uint16_t)0x0001) |
Filter Init Mode bit 0
Definition at line 1825 of file stm32f4xx.h.
| #define CAN_FM1R_FBM1 ((uint16_t)0x0002) |
Filter Init Mode bit 1
Definition at line 1826 of file stm32f4xx.h.
| #define CAN_FM1R_FBM10 ((uint16_t)0x0400) |
Filter Init Mode bit 10
Definition at line 1835 of file stm32f4xx.h.
| #define CAN_FM1R_FBM11 ((uint16_t)0x0800) |
Filter Init Mode bit 11
Definition at line 1836 of file stm32f4xx.h.
| #define CAN_FM1R_FBM12 ((uint16_t)0x1000) |
Filter Init Mode bit 12
Definition at line 1837 of file stm32f4xx.h.
| #define CAN_FM1R_FBM13 ((uint16_t)0x2000) |
Filter Init Mode bit 13
Definition at line 1838 of file stm32f4xx.h.
| #define CAN_FM1R_FBM2 ((uint16_t)0x0004) |
Filter Init Mode bit 2
Definition at line 1827 of file stm32f4xx.h.
| #define CAN_FM1R_FBM3 ((uint16_t)0x0008) |
Filter Init Mode bit 3
Definition at line 1828 of file stm32f4xx.h.
| #define CAN_FM1R_FBM4 ((uint16_t)0x0010) |
Filter Init Mode bit 4
Definition at line 1829 of file stm32f4xx.h.
| #define CAN_FM1R_FBM5 ((uint16_t)0x0020) |
Filter Init Mode bit 5
Definition at line 1830 of file stm32f4xx.h.
| #define CAN_FM1R_FBM6 ((uint16_t)0x0040) |
Filter Init Mode bit 6
Definition at line 1831 of file stm32f4xx.h.
| #define CAN_FM1R_FBM7 ((uint16_t)0x0080) |
Filter Init Mode bit 7
Definition at line 1832 of file stm32f4xx.h.
| #define CAN_FM1R_FBM8 ((uint16_t)0x0100) |
Filter Init Mode bit 8
Definition at line 1833 of file stm32f4xx.h.
| #define CAN_FM1R_FBM9 ((uint16_t)0x0200) |
Filter Init Mode bit 9
Definition at line 1834 of file stm32f4xx.h.
| #define CAN_FMR_FINIT ((uint8_t)0x01) |
Filter Init Mode
Definition at line 1821 of file stm32f4xx.h.
| #define CAN_FS1R_FSC ((uint16_t)0x3FFF) |
Filter Scale Configuration
Definition at line 1841 of file stm32f4xx.h.
| #define CAN_FS1R_FSC0 ((uint16_t)0x0001) |
Filter Scale Configuration bit 0
Definition at line 1842 of file stm32f4xx.h.
| #define CAN_FS1R_FSC1 ((uint16_t)0x0002) |
Filter Scale Configuration bit 1
Definition at line 1843 of file stm32f4xx.h.
| #define CAN_FS1R_FSC10 ((uint16_t)0x0400) |
Filter Scale Configuration bit 10
Definition at line 1852 of file stm32f4xx.h.
| #define CAN_FS1R_FSC11 ((uint16_t)0x0800) |
Filter Scale Configuration bit 11
Definition at line 1853 of file stm32f4xx.h.
| #define CAN_FS1R_FSC12 ((uint16_t)0x1000) |
Filter Scale Configuration bit 12
Definition at line 1854 of file stm32f4xx.h.
| #define CAN_FS1R_FSC13 ((uint16_t)0x2000) |
Filter Scale Configuration bit 13
Definition at line 1855 of file stm32f4xx.h.
| #define CAN_FS1R_FSC2 ((uint16_t)0x0004) |
Filter Scale Configuration bit 2
Definition at line 1844 of file stm32f4xx.h.
| #define CAN_FS1R_FSC3 ((uint16_t)0x0008) |
Filter Scale Configuration bit 3
Definition at line 1845 of file stm32f4xx.h.
| #define CAN_FS1R_FSC4 ((uint16_t)0x0010) |
Filter Scale Configuration bit 4
Definition at line 1846 of file stm32f4xx.h.
| #define CAN_FS1R_FSC5 ((uint16_t)0x0020) |
Filter Scale Configuration bit 5
Definition at line 1847 of file stm32f4xx.h.
| #define CAN_FS1R_FSC6 ((uint16_t)0x0040) |
Filter Scale Configuration bit 6
Definition at line 1848 of file stm32f4xx.h.
| #define CAN_FS1R_FSC7 ((uint16_t)0x0080) |
Filter Scale Configuration bit 7
Definition at line 1849 of file stm32f4xx.h.
| #define CAN_FS1R_FSC8 ((uint16_t)0x0100) |
Filter Scale Configuration bit 8
Definition at line 1850 of file stm32f4xx.h.
| #define CAN_FS1R_FSC9 ((uint16_t)0x0200) |
Filter Scale Configuration bit 9
Definition at line 1851 of file stm32f4xx.h.
| #define CAN_IER_BOFIE ((uint32_t)0x00000400) |
Bus-Off Interrupt Enable
Definition at line 1673 of file stm32f4xx.h.
| #define CAN_IER_EPVIE ((uint32_t)0x00000200) |
Error Passive Interrupt Enable
Definition at line 1672 of file stm32f4xx.h.
| #define CAN_IER_ERRIE ((uint32_t)0x00008000) |
Error Interrupt Enable
Definition at line 1675 of file stm32f4xx.h.
| #define CAN_IER_EWGIE ((uint32_t)0x00000100) |
Error Warning Interrupt Enable
Definition at line 1671 of file stm32f4xx.h.
| #define CAN_IER_FFIE0 ((uint32_t)0x00000004) |
FIFO Full Interrupt Enable
Definition at line 1666 of file stm32f4xx.h.
| #define CAN_IER_FFIE1 ((uint32_t)0x00000020) |
FIFO Full Interrupt Enable
Definition at line 1669 of file stm32f4xx.h.
| #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
FIFO Message Pending Interrupt Enable
Definition at line 1665 of file stm32f4xx.h.
| #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
FIFO Message Pending Interrupt Enable
Definition at line 1668 of file stm32f4xx.h.
| #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
FIFO Overrun Interrupt Enable
Definition at line 1667 of file stm32f4xx.h.
| #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
FIFO Overrun Interrupt Enable
Definition at line 1670 of file stm32f4xx.h.
| #define CAN_IER_LECIE ((uint32_t)0x00000800) |
Last Error Code Interrupt Enable
Definition at line 1674 of file stm32f4xx.h.
| #define CAN_IER_SLKIE ((uint32_t)0x00020000) |
Sleep Interrupt Enable
Definition at line 1677 of file stm32f4xx.h.
| #define CAN_IER_TMEIE ((uint32_t)0x00000001) |
Transmit Mailbox Empty Interrupt Enable
Definition at line 1664 of file stm32f4xx.h.
| #define CAN_IER_WKUIE ((uint32_t)0x00010000) |
Wakeup Interrupt Enable
Definition at line 1676 of file stm32f4xx.h.
| #define CAN_MCR_ABOM ((uint16_t)0x0040) |
Automatic Bus-Off Management
Definition at line 1608 of file stm32f4xx.h.
| #define CAN_MCR_AWUM ((uint16_t)0x0020) |
Automatic Wakeup Mode
Definition at line 1607 of file stm32f4xx.h.
| #define CAN_MCR_INRQ ((uint16_t)0x0001) |
<CAN control and status registers Initialization Request
Definition at line 1602 of file stm32f4xx.h.
| #define CAN_MCR_NART ((uint16_t)0x0010) |
No Automatic Retransmission
Definition at line 1606 of file stm32f4xx.h.
| #define CAN_MCR_RESET ((uint16_t)0x8000) |
bxCAN software master reset
Definition at line 1610 of file stm32f4xx.h.
| #define CAN_MCR_RFLM ((uint16_t)0x0008) |
Receive FIFO Locked Mode
Definition at line 1605 of file stm32f4xx.h.
| #define CAN_MCR_SLEEP ((uint16_t)0x0002) |
Sleep Mode Request
Definition at line 1603 of file stm32f4xx.h.
| #define CAN_MCR_TTCM ((uint16_t)0x0080) |
Time Triggered Communication Mode
Definition at line 1609 of file stm32f4xx.h.
| #define CAN_MCR_TXFP ((uint16_t)0x0004) |
Transmit FIFO Priority
Definition at line 1604 of file stm32f4xx.h.
| #define CAN_MSR_ERRI ((uint16_t)0x0004) |
Error Interrupt
Definition at line 1615 of file stm32f4xx.h.
| #define CAN_MSR_INAK ((uint16_t)0x0001) |
Initialization Acknowledge
Definition at line 1613 of file stm32f4xx.h.
| #define CAN_MSR_RX ((uint16_t)0x0800) |
CAN Rx Signal
Definition at line 1621 of file stm32f4xx.h.
| #define CAN_MSR_RXM ((uint16_t)0x0200) |
Receive Mode
Definition at line 1619 of file stm32f4xx.h.
| #define CAN_MSR_SAMP ((uint16_t)0x0400) |
Last Sample Point
Definition at line 1620 of file stm32f4xx.h.
| #define CAN_MSR_SLAK ((uint16_t)0x0002) |
Sleep Acknowledge
Definition at line 1614 of file stm32f4xx.h.
| #define CAN_MSR_SLAKI ((uint16_t)0x0010) |
Sleep Acknowledge Interrupt
Definition at line 1617 of file stm32f4xx.h.
| #define CAN_MSR_TXM ((uint16_t)0x0100) |
Transmit Mode
Definition at line 1618 of file stm32f4xx.h.
| #define CAN_MSR_WKUI ((uint16_t)0x0008) |
Wakeup Interrupt
Definition at line 1616 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 1791 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 1792 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 1793 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 1794 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 1814 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 1815 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 1816 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7 CAN filter registers
Definition at line 1817 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 1785 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 1786 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 1787 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 1788 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 1808 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 1809 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 1810 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 1811 of file stm32f4xx.h.
| #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 1780 of file stm32f4xx.h.
| #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
Filter Match Index
Definition at line 1781 of file stm32f4xx.h.
| #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 1782 of file stm32f4xx.h.
| #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 1803 of file stm32f4xx.h.
| #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
Filter Match Index
Definition at line 1804 of file stm32f4xx.h.
| #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 1805 of file stm32f4xx.h.
| #define CAN_RF0R_FMP0 ((uint8_t)0x03) |
FIFO 0 Message Pending
Definition at line 1652 of file stm32f4xx.h.
| #define CAN_RF0R_FOVR0 ((uint8_t)0x10) |
FIFO 0 Overrun
Definition at line 1654 of file stm32f4xx.h.
| #define CAN_RF0R_FULL0 ((uint8_t)0x08) |
FIFO 0 Full
Definition at line 1653 of file stm32f4xx.h.
| #define CAN_RF0R_RFOM0 ((uint8_t)0x20) |
Release FIFO 0 Output Mailbox
Definition at line 1655 of file stm32f4xx.h.
| #define CAN_RF1R_FMP1 ((uint8_t)0x03) |
FIFO 1 Message Pending
Definition at line 1658 of file stm32f4xx.h.
| #define CAN_RF1R_FOVR1 ((uint8_t)0x10) |
FIFO 1 Overrun
Definition at line 1660 of file stm32f4xx.h.
| #define CAN_RF1R_FULL1 ((uint8_t)0x08) |
FIFO 1 Full
Definition at line 1659 of file stm32f4xx.h.
| #define CAN_RF1R_RFOM1 ((uint8_t)0x20) |
Release FIFO 1 Output Mailbox
Definition at line 1661 of file stm32f4xx.h.
| #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 1776 of file stm32f4xx.h.
| #define CAN_RI0R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 1775 of file stm32f4xx.h.
| #define CAN_RI0R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 1774 of file stm32f4xx.h.
| #define CAN_RI0R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 1777 of file stm32f4xx.h.
| #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
Extended identifier
Definition at line 1799 of file stm32f4xx.h.
| #define CAN_RI1R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 1798 of file stm32f4xx.h.
| #define CAN_RI1R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 1797 of file stm32f4xx.h.
| #define CAN_RI1R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 1800 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 1720 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 1721 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 1722 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 1723 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 1744 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 1745 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 1746 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 1747 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 1768 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 1769 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 1770 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 1771 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 1714 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 1715 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 1716 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 1717 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 1738 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 1739 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 1740 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 1741 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 1762 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 1763 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 1764 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 1765 of file stm32f4xx.h.
| #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 1709 of file stm32f4xx.h.
| #define CAN_TDT0R_TGT ((uint32_t)0x00000100) |
Transmit Global Time
Definition at line 1710 of file stm32f4xx.h.
| #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 1711 of file stm32f4xx.h.
| #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 1733 of file stm32f4xx.h.
| #define CAN_TDT1R_TGT ((uint32_t)0x00000100) |
Transmit Global Time
Definition at line 1734 of file stm32f4xx.h.
| #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 1735 of file stm32f4xx.h.
| #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 1757 of file stm32f4xx.h.
| #define CAN_TDT2R_TGT ((uint32_t)0x00000100) |
Transmit Global Time
Definition at line 1758 of file stm32f4xx.h.
| #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 1759 of file stm32f4xx.h.
| #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 1705 of file stm32f4xx.h.
| #define CAN_TI0R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 1704 of file stm32f4xx.h.
| #define CAN_TI0R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 1703 of file stm32f4xx.h.
| #define CAN_TI0R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 1706 of file stm32f4xx.h.
| #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 1702 of file stm32f4xx.h.
| #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 1729 of file stm32f4xx.h.
| #define CAN_TI1R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 1728 of file stm32f4xx.h.
| #define CAN_TI1R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 1727 of file stm32f4xx.h.
| #define CAN_TI1R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 1730 of file stm32f4xx.h.
| #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 1726 of file stm32f4xx.h.
| #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
Extended identifier
Definition at line 1753 of file stm32f4xx.h.
| #define CAN_TI2R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 1752 of file stm32f4xx.h.
| #define CAN_TI2R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 1751 of file stm32f4xx.h.
| #define CAN_TI2R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 1754 of file stm32f4xx.h.
| #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 1750 of file stm32f4xx.h.
| #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
Abort Request for Mailbox0
Definition at line 1628 of file stm32f4xx.h.
| #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
Abort Request for Mailbox 1
Definition at line 1633 of file stm32f4xx.h.
| #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
Abort Request for Mailbox 2
Definition at line 1638 of file stm32f4xx.h.
| #define CAN_TSR_ALST0 ((uint32_t)0x00000004) |
Arbitration Lost for Mailbox0
Definition at line 1626 of file stm32f4xx.h.
| #define CAN_TSR_ALST1 ((uint32_t)0x00000400) |
Arbitration Lost for Mailbox1
Definition at line 1631 of file stm32f4xx.h.
| #define CAN_TSR_ALST2 ((uint32_t)0x00040000) |
Arbitration Lost for mailbox 2
Definition at line 1636 of file stm32f4xx.h.
| #define CAN_TSR_CODE ((uint32_t)0x03000000) |
Mailbox Code
Definition at line 1639 of file stm32f4xx.h.
| #define CAN_TSR_LOW ((uint32_t)0xE0000000) |
LOW[2:0] bits
Definition at line 1646 of file stm32f4xx.h.
| #define CAN_TSR_LOW0 ((uint32_t)0x20000000) |
Lowest Priority Flag for Mailbox 0
Definition at line 1647 of file stm32f4xx.h.
| #define CAN_TSR_LOW1 ((uint32_t)0x40000000) |
Lowest Priority Flag for Mailbox 1
Definition at line 1648 of file stm32f4xx.h.
| #define CAN_TSR_LOW2 ((uint32_t)0x80000000) |
Lowest Priority Flag for Mailbox 2
Definition at line 1649 of file stm32f4xx.h.
| #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
Request Completed Mailbox0
Definition at line 1624 of file stm32f4xx.h.
| #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
Request Completed Mailbox1
Definition at line 1629 of file stm32f4xx.h.
| #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
Request Completed Mailbox2
Definition at line 1634 of file stm32f4xx.h.
| #define CAN_TSR_TERR0 ((uint32_t)0x00000008) |
Transmission Error of Mailbox0
Definition at line 1627 of file stm32f4xx.h.
| #define CAN_TSR_TERR1 ((uint32_t)0x00000800) |
Transmission Error of Mailbox1
Definition at line 1632 of file stm32f4xx.h.
| #define CAN_TSR_TERR2 ((uint32_t)0x00080000) |
Transmission Error of Mailbox 2
Definition at line 1637 of file stm32f4xx.h.
| #define CAN_TSR_TME ((uint32_t)0x1C000000) |
TME[2:0] bits
Definition at line 1641 of file stm32f4xx.h.
| #define CAN_TSR_TME0 ((uint32_t)0x04000000) |
Transmit Mailbox 0 Empty
Definition at line 1642 of file stm32f4xx.h.
| #define CAN_TSR_TME1 ((uint32_t)0x08000000) |
Transmit Mailbox 1 Empty
Definition at line 1643 of file stm32f4xx.h.
| #define CAN_TSR_TME2 ((uint32_t)0x10000000) |
Transmit Mailbox 2 Empty
Definition at line 1644 of file stm32f4xx.h.
| #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
Transmission OK of Mailbox0
Definition at line 1625 of file stm32f4xx.h.
| #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
Transmission OK of Mailbox1
Definition at line 1630 of file stm32f4xx.h.
| #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
Transmission OK of Mailbox 2
Definition at line 1635 of file stm32f4xx.h.
| #define CRC_CR_RESET ((uint8_t)0x01) |
RESET bit
Definition at line 2857 of file stm32f4xx.h.
| #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
Data register bits
Definition at line 2849 of file stm32f4xx.h.
| #define CRC_IDR_IDR ((uint8_t)0xFF) |
General-purpose 8-bit data register bits
Definition at line 2853 of file stm32f4xx.h.
| #define CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
Definition at line 2865 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE ((uint32_t)0x00000038) |
Definition at line 2867 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
Definition at line 2868 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
Definition at line 2869 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
Definition at line 2870 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
Definition at line 2876 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
Definition at line 2877 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
Definition at line 2875 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
Definition at line 2878 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
Definition at line 2874 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
Definition at line 2873 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
Definition at line 2872 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
Definition at line 2871 of file stm32f4xx.h.
| #define CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
Definition at line 2887 of file stm32f4xx.h.
| #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
Definition at line 2880 of file stm32f4xx.h.
| #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
Definition at line 2881 of file stm32f4xx.h.
| #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
Definition at line 2882 of file stm32f4xx.h.
| #define CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
Definition at line 2886 of file stm32f4xx.h.
| #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
Definition at line 2883 of file stm32f4xx.h.
| #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
Definition at line 2884 of file stm32f4xx.h.
| #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
Definition at line 2885 of file stm32f4xx.h.
| #define CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
Definition at line 2895 of file stm32f4xx.h.
| #define CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
Definition at line 2896 of file stm32f4xx.h.
| #define CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
Definition at line 2898 of file stm32f4xx.h.
| #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
Definition at line 2899 of file stm32f4xx.h.
| #define CRYP_MISR_INMIS ((uint32_t)0x00000001) |
Definition at line 2904 of file stm32f4xx.h.
| #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
Definition at line 2905 of file stm32f4xx.h.
| #define CRYP_RISR_INRIS ((uint32_t)0x00000002) |
Definition at line 2902 of file stm32f4xx.h.
| #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
Definition at line 2901 of file stm32f4xx.h.
| #define CRYP_SR_BUSY ((uint32_t)0x00000010) |
Definition at line 2893 of file stm32f4xx.h.
| #define CRYP_SR_IFEM ((uint32_t)0x00000001) |
Definition at line 2889 of file stm32f4xx.h.
| #define CRYP_SR_IFNF ((uint32_t)0x00000002) |
Definition at line 2890 of file stm32f4xx.h.
| #define CRYP_SR_OFFU ((uint32_t)0x00000008) |
Definition at line 2892 of file stm32f4xx.h.
| #define CRYP_SR_OFNE ((uint32_t)0x00000004) |
Definition at line 2891 of file stm32f4xx.h.
| #define DAC_CR_BOFF1 ((uint32_t)0x00000002) |
DAC channel1 output buffer disable
Definition at line 2914 of file stm32f4xx.h.
| #define DAC_CR_BOFF2 ((uint32_t)0x00020000) |
DAC channel2 output buffer disable
Definition at line 2934 of file stm32f4xx.h.
| #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
DAC channel1 DMA enable
Definition at line 2932 of file stm32f4xx.h.
| #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
DAC channel2 DMA enabled
Definition at line 2952 of file stm32f4xx.h.
| #define DAC_CR_EN1 ((uint32_t)0x00000001) |
DAC channel1 enable
Definition at line 2913 of file stm32f4xx.h.
| #define DAC_CR_EN2 ((uint32_t)0x00010000) |
DAC channel2 enable
Definition at line 2933 of file stm32f4xx.h.
| #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
Definition at line 2926 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 2927 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 2928 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 2929 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 2930 of file stm32f4xx.h.
| #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
Definition at line 2946 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 2947 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 2948 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 2949 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 2950 of file stm32f4xx.h.
| #define DAC_CR_TEN1 ((uint32_t)0x00000004) |
DAC channel1 Trigger enable
Definition at line 2915 of file stm32f4xx.h.
| #define DAC_CR_TEN2 ((uint32_t)0x00040000) |
DAC channel2 Trigger enable
Definition at line 2935 of file stm32f4xx.h.
| #define DAC_CR_TSEL1 ((uint32_t)0x00000038) |
TSEL1[2:0] (DAC channel1 Trigger selection)
Definition at line 2917 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 2918 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 2919 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 2920 of file stm32f4xx.h.
| #define DAC_CR_TSEL2 ((uint32_t)0x00380000) |
TSEL2[2:0] (DAC channel2 Trigger selection)
Definition at line 2937 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
Bit 0
Definition at line 2938 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
Bit 1
Definition at line 2939 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
Bit 2
Definition at line 2940 of file stm32f4xx.h.
| #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
Definition at line 2922 of file stm32f4xx.h.
| #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 2923 of file stm32f4xx.h.
| #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 2924 of file stm32f4xx.h.
| #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
Definition at line 2942 of file stm32f4xx.h.
| #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
Bit 0
Definition at line 2943 of file stm32f4xx.h.
| #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
Bit 1
Definition at line 2944 of file stm32f4xx.h.
| #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
DAC channel1 12-bit Left aligned data
Definition at line 2962 of file stm32f4xx.h.
| #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
DAC channel2 12-bit Left aligned data
Definition at line 2971 of file stm32f4xx.h.
| #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
DAC channel1 12-bit Left aligned data
Definition at line 2981 of file stm32f4xx.h.
| #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
DAC channel2 12-bit Left aligned data
Definition at line 2982 of file stm32f4xx.h.
| #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
DAC channel1 12-bit Right aligned data
Definition at line 2959 of file stm32f4xx.h.
| #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
DAC channel2 12-bit Right aligned data
Definition at line 2968 of file stm32f4xx.h.
| #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
DAC channel1 12-bit Right aligned data
Definition at line 2977 of file stm32f4xx.h.
| #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
DAC channel2 12-bit Right aligned data
Definition at line 2978 of file stm32f4xx.h.
| #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
DAC channel1 8-bit Right aligned data
Definition at line 2965 of file stm32f4xx.h.
| #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
DAC channel2 8-bit Right aligned data
Definition at line 2974 of file stm32f4xx.h.
| #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
DAC channel1 8-bit Right aligned data
Definition at line 2985 of file stm32f4xx.h.
| #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
DAC channel2 8-bit Right aligned data
Definition at line 2986 of file stm32f4xx.h.
| #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
DAC channel1 data output
Definition at line 2989 of file stm32f4xx.h.
| #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
DAC channel2 data output
Definition at line 2992 of file stm32f4xx.h.
| #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
DAC channel1 DMA underrun flag
Definition at line 2995 of file stm32f4xx.h.
| #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
DAC channel2 DMA underrun flag
Definition at line 2996 of file stm32f4xx.h.
| #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
DAC channel1 software trigger
Definition at line 2955 of file stm32f4xx.h.
| #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
DAC channel2 software trigger
Definition at line 2956 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
Definition at line 6506 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
Definition at line 6507 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
Definition at line 6503 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
Definition at line 6504 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
Definition at line 6505 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
Definition at line 6509 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
Definition at line 6502 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
Definition at line 6500 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
Definition at line 6515 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
Definition at line 6516 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
Definition at line 6497 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
Definition at line 6498 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
Definition at line 6499 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
Definition at line 6512 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
Definition at line 6491 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
Definition at line 6492 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
Definition at line 6493 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
Definition at line 6494 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
Definition at line 6495 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
Definition at line 6496 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
Definition at line 6513 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
Definition at line 6514 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
Definition at line 6501 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
Definition at line 6481 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
Definition at line 6483 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
Definition at line 6482 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
Definition at line 6484 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
Definition at line 6486 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040 |
Bit 0
Definition at line 6487 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080 |
Bit 1
Definition at line 6488 of file stm32f4xx.h.
| #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
Definition at line 6477 of file stm32f4xx.h.
| #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
Definition at line 6478 of file stm32f4xx.h.
| #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
Definition at line 3010 of file stm32f4xx.h.
| #define DCMI_CR_CM ((uint32_t)0x00000002) |
Definition at line 3011 of file stm32f4xx.h.
| #define DCMI_CR_CRE ((uint32_t)0x00001000) |
Definition at line 3022 of file stm32f4xx.h.
| #define DCMI_CR_CROP ((uint32_t)0x00000004) |
Definition at line 3012 of file stm32f4xx.h.
| #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
Definition at line 3020 of file stm32f4xx.h.
| #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
Definition at line 3021 of file stm32f4xx.h.
| #define DCMI_CR_ENABLE ((uint32_t)0x00004000) |
Definition at line 3023 of file stm32f4xx.h.
| #define DCMI_CR_ESS ((uint32_t)0x00000010) |
Definition at line 3014 of file stm32f4xx.h.
| #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
Definition at line 3018 of file stm32f4xx.h.
| #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
Definition at line 3019 of file stm32f4xx.h.
| #define DCMI_CR_HSPOL ((uint32_t)0x00000040) |
Definition at line 3016 of file stm32f4xx.h.
| #define DCMI_CR_JPEG ((uint32_t)0x00000008) |
Definition at line 3013 of file stm32f4xx.h.
| #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
Definition at line 3015 of file stm32f4xx.h.
| #define DCMI_CR_VSPOL ((uint32_t)0x00000080) |
Definition at line 3017 of file stm32f4xx.h.
| #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
Definition at line 3054 of file stm32f4xx.h.
| #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
Definition at line 3052 of file stm32f4xx.h.
| #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
Definition at line 3056 of file stm32f4xx.h.
| #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) |
Definition at line 3053 of file stm32f4xx.h.
| #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
Definition at line 3055 of file stm32f4xx.h.
| #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
Definition at line 3040 of file stm32f4xx.h.
| #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
Definition at line 3038 of file stm32f4xx.h.
| #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
Definition at line 3042 of file stm32f4xx.h.
| #define DCMI_IER_OVF_IE ((uint32_t)0x00000002) |
Definition at line 3039 of file stm32f4xx.h.
| #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
Definition at line 3041 of file stm32f4xx.h.
| #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) |
Definition at line 3047 of file stm32f4xx.h.
| #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) |
Definition at line 3045 of file stm32f4xx.h.
| #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) |
Definition at line 3049 of file stm32f4xx.h.
| #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) |
Definition at line 3046 of file stm32f4xx.h.
| #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) |
Definition at line 3048 of file stm32f4xx.h.
| #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) |
Definition at line 3033 of file stm32f4xx.h.
| #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) |
Definition at line 3031 of file stm32f4xx.h.
| #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) |
Definition at line 3035 of file stm32f4xx.h.
| #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) |
Definition at line 3032 of file stm32f4xx.h.
| #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) |
Definition at line 3034 of file stm32f4xx.h.
| #define DCMI_SR_FNE ((uint32_t)0x00000004) |
Definition at line 3028 of file stm32f4xx.h.
| #define DCMI_SR_HSYNC ((uint32_t)0x00000001) |
Definition at line 3026 of file stm32f4xx.h.
| #define DCMI_SR_VSYNC ((uint32_t)0x00000002) |
Definition at line 3027 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
Definition at line 3215 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
Definition at line 3210 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
Definition at line 3205 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
Definition at line 3200 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
Definition at line 3216 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
Definition at line 3211 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
Definition at line 3206 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
Definition at line 3201 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
Definition at line 3213 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
Definition at line 3208 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
Definition at line 3203 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
Definition at line 3198 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
Definition at line 3212 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
Definition at line 3207 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
Definition at line 3202 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
Definition at line 3197 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
Definition at line 3214 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
Definition at line 3209 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
Definition at line 3204 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
Definition at line 3199 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
Definition at line 3171 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
Definition at line 3166 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
Definition at line 3161 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
Definition at line 3156 of file stm32f4xx.h.
| #define DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
Definition at line 3172 of file stm32f4xx.h.
| #define DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
Definition at line 3167 of file stm32f4xx.h.
| #define DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
Definition at line 3162 of file stm32f4xx.h.
| #define DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
Definition at line 3157 of file stm32f4xx.h.
| #define DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
Definition at line 3169 of file stm32f4xx.h.
| #define DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
Definition at line 3164 of file stm32f4xx.h.
| #define DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
Definition at line 3159 of file stm32f4xx.h.
| #define DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
Definition at line 3154 of file stm32f4xx.h.
| #define DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
Definition at line 3168 of file stm32f4xx.h.
| #define DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
Definition at line 3163 of file stm32f4xx.h.
| #define DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
Definition at line 3158 of file stm32f4xx.h.
| #define DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
Definition at line 3153 of file stm32f4xx.h.
| #define DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
Definition at line 3170 of file stm32f4xx.h.
| #define DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
Definition at line 3165 of file stm32f4xx.h.
| #define DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
Definition at line 3160 of file stm32f4xx.h.
| #define DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
Definition at line 3155 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
Definition at line 3193 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
Definition at line 3188 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
Definition at line 3183 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
Definition at line 3178 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
Definition at line 3194 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
Definition at line 3189 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
Definition at line 3184 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
Definition at line 3179 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
Definition at line 3191 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
Definition at line 3186 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
Definition at line 3181 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
Definition at line 3176 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
Definition at line 3190 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
Definition at line 3185 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
Definition at line 3180 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
Definition at line 3175 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
Definition at line 3192 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
Definition at line 3187 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
Definition at line 3182 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
Definition at line 3177 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
Definition at line 3149 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
Definition at line 3144 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
Definition at line 3139 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
Definition at line 3134 of file stm32f4xx.h.
| #define DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
Definition at line 3150 of file stm32f4xx.h.
| #define DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
Definition at line 3145 of file stm32f4xx.h.
| #define DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
Definition at line 3140 of file stm32f4xx.h.
| #define DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
Definition at line 3135 of file stm32f4xx.h.
| #define DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
Definition at line 3147 of file stm32f4xx.h.
| #define DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
Definition at line 3142 of file stm32f4xx.h.
| #define DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
Definition at line 3137 of file stm32f4xx.h.
| #define DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
Definition at line 3132 of file stm32f4xx.h.
| #define DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
Definition at line 3146 of file stm32f4xx.h.
| #define DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
Definition at line 3141 of file stm32f4xx.h.
| #define DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
Definition at line 3136 of file stm32f4xx.h.
| #define DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
Definition at line 3131 of file stm32f4xx.h.
| #define DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
Definition at line 3148 of file stm32f4xx.h.
| #define DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
Definition at line 3143 of file stm32f4xx.h.
| #define DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
Definition at line 3138 of file stm32f4xx.h.
| #define DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
Definition at line 3133 of file stm32f4xx.h.
| #define DMA_SxCR_ACK ((uint32_t)0x00100000) |
Definition at line 3074 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
Definition at line 3064 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
Definition at line 3065 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
Definition at line 3066 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
Definition at line 3067 of file stm32f4xx.h.
| #define DMA_SxCR_CIRC ((uint32_t)0x00000100) |
Definition at line 3089 of file stm32f4xx.h.
| #define DMA_SxCR_CT ((uint32_t)0x00080000) |
Definition at line 3075 of file stm32f4xx.h.
| #define DMA_SxCR_DBM ((uint32_t)0x00040000) |
Definition at line 3076 of file stm32f4xx.h.
| #define DMA_SxCR_DIR ((uint32_t)0x000000C0) |
Definition at line 3090 of file stm32f4xx.h.
| #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
Definition at line 3091 of file stm32f4xx.h.
| #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
Definition at line 3092 of file stm32f4xx.h.
| #define DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
Definition at line 3097 of file stm32f4xx.h.
| #define DMA_SxCR_EN ((uint32_t)0x00000001) |
Definition at line 3098 of file stm32f4xx.h.
| #define DMA_SxCR_HTIE ((uint32_t)0x00000008) |
Definition at line 3095 of file stm32f4xx.h.
| #define DMA_SxCR_MBURST ((uint32_t)0x01800000) |
Definition at line 3068 of file stm32f4xx.h.
| #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
Definition at line 3069 of file stm32f4xx.h.
| #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
Definition at line 3070 of file stm32f4xx.h.
| #define DMA_SxCR_MINC ((uint32_t)0x00000400) |
Definition at line 3087 of file stm32f4xx.h.
| #define DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
Definition at line 3081 of file stm32f4xx.h.
| #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
Definition at line 3082 of file stm32f4xx.h.
| #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
Definition at line 3083 of file stm32f4xx.h.
| #define DMA_SxCR_PBURST ((uint32_t)0x00600000) |
Definition at line 3071 of file stm32f4xx.h.
| #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
Definition at line 3072 of file stm32f4xx.h.
| #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
Definition at line 3073 of file stm32f4xx.h.
| #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
Definition at line 3093 of file stm32f4xx.h.
| #define DMA_SxCR_PINC ((uint32_t)0x00000200) |
Definition at line 3088 of file stm32f4xx.h.
| #define DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
Definition at line 3080 of file stm32f4xx.h.
| #define DMA_SxCR_PL ((uint32_t)0x00030000) |
Definition at line 3077 of file stm32f4xx.h.
| #define DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
Definition at line 3078 of file stm32f4xx.h.
| #define DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
Definition at line 3079 of file stm32f4xx.h.
| #define DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
Definition at line 3084 of file stm32f4xx.h.
| #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
Definition at line 3085 of file stm32f4xx.h.
| #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
Definition at line 3086 of file stm32f4xx.h.
| #define DMA_SxCR_TCIE ((uint32_t)0x00000010) |
Definition at line 3094 of file stm32f4xx.h.
| #define DMA_SxCR_TEIE ((uint32_t)0x00000004) |
Definition at line 3096 of file stm32f4xx.h.
| #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
Definition at line 3125 of file stm32f4xx.h.
| #define DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
Definition at line 3120 of file stm32f4xx.h.
| #define DMA_SxFCR_FS ((uint32_t)0x00000038) |
Definition at line 3121 of file stm32f4xx.h.
| #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
Definition at line 3122 of file stm32f4xx.h.
| #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
Definition at line 3123 of file stm32f4xx.h.
| #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
Definition at line 3124 of file stm32f4xx.h.
| #define DMA_SxFCR_FTH ((uint32_t)0x00000003) |
Definition at line 3126 of file stm32f4xx.h.
| #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
Definition at line 3127 of file stm32f4xx.h.
| #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
Definition at line 3128 of file stm32f4xx.h.
| #define DMA_SxNDT ((uint32_t)0x0000FFFF) |
Definition at line 3101 of file stm32f4xx.h.
| #define DMA_SxNDT_0 ((uint32_t)0x00000001) |
Definition at line 3102 of file stm32f4xx.h.
| #define DMA_SxNDT_1 ((uint32_t)0x00000002) |
Definition at line 3103 of file stm32f4xx.h.
| #define DMA_SxNDT_10 ((uint32_t)0x00000400) |
Definition at line 3112 of file stm32f4xx.h.
| #define DMA_SxNDT_11 ((uint32_t)0x00000800) |
Definition at line 3113 of file stm32f4xx.h.
| #define DMA_SxNDT_12 ((uint32_t)0x00001000) |
Definition at line 3114 of file stm32f4xx.h.
| #define DMA_SxNDT_13 ((uint32_t)0x00002000) |
Definition at line 3115 of file stm32f4xx.h.
| #define DMA_SxNDT_14 ((uint32_t)0x00004000) |
Definition at line 3116 of file stm32f4xx.h.
| #define DMA_SxNDT_15 ((uint32_t)0x00008000) |
Definition at line 3117 of file stm32f4xx.h.
| #define DMA_SxNDT_2 ((uint32_t)0x00000004) |
Definition at line 3104 of file stm32f4xx.h.
| #define DMA_SxNDT_3 ((uint32_t)0x00000008) |
Definition at line 3105 of file stm32f4xx.h.
| #define DMA_SxNDT_4 ((uint32_t)0x00000010) |
Definition at line 3106 of file stm32f4xx.h.
| #define DMA_SxNDT_5 ((uint32_t)0x00000020) |
Definition at line 3107 of file stm32f4xx.h.
| #define DMA_SxNDT_6 ((uint32_t)0x00000040) |
Definition at line 3108 of file stm32f4xx.h.
| #define DMA_SxNDT_7 ((uint32_t)0x00000080) |
Definition at line 3109 of file stm32f4xx.h.
| #define DMA_SxNDT_8 ((uint32_t)0x00000100) |
Definition at line 3110 of file stm32f4xx.h.
| #define DMA_SxNDT_9 ((uint32_t)0x00000200) |
Definition at line 3111 of file stm32f4xx.h.
| #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
Definition at line 6798 of file stm32f4xx.h.
| #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
Definition at line 6835 of file stm32f4xx.h.
| #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
Definition at line 6834 of file stm32f4xx.h.
| #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
Definition at line 6833 of file stm32f4xx.h.
| #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
Definition at line 6814 of file stm32f4xx.h.
| #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
Definition at line 6799 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
Definition at line 6820 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 6825 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
Definition at line 6821 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
Definition at line 6822 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 6826 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 6823 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
Definition at line 6832 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 6829 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 6830 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 6827 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
Definition at line 6831 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 6828 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 6824 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
Definition at line 6801 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 6806 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
Definition at line 6802 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
Definition at line 6803 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 6807 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 6804 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
Definition at line 6813 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 6810 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 6811 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 6808 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
Definition at line 6812 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 6809 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 6805 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
Definition at line 6815 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
Definition at line 6816 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
Definition at line 6817 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
Definition at line 6818 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
Definition at line 6819 of file stm32f4xx.h.
| #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
Definition at line 6836 of file stm32f4xx.h.
| #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
Definition at line 6800 of file stm32f4xx.h.
| #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
Definition at line 6948 of file stm32f4xx.h.
| #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
Definition at line 6942 of file stm32f4xx.h.
| #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
Definition at line 6945 of file stm32f4xx.h.
| #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
Definition at line 6939 of file stm32f4xx.h.
| #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
Definition at line 6917 of file stm32f4xx.h.
| #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
Definition at line 6918 of file stm32f4xx.h.
| #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
Definition at line 6920 of file stm32f4xx.h.
| #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
Definition at line 6919 of file stm32f4xx.h.
| #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
Definition at line 6916 of file stm32f4xx.h.
| #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
Definition at line 6923 of file stm32f4xx.h.
| #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
Definition at line 6924 of file stm32f4xx.h.
| #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
Definition at line 6926 of file stm32f4xx.h.
| #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
Definition at line 6922 of file stm32f4xx.h.
| #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
Definition at line 6921 of file stm32f4xx.h.
| #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
Definition at line 6928 of file stm32f4xx.h.
| #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
Definition at line 6930 of file stm32f4xx.h.
| #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
Definition at line 6927 of file stm32f4xx.h.
| #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
Definition at line 6929 of file stm32f4xx.h.
| #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
Definition at line 6925 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
Definition at line 6934 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
Definition at line 6936 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
Definition at line 6933 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
Definition at line 6935 of file stm32f4xx.h.
| #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
Definition at line 6892 of file stm32f4xx.h.
| #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
Definition at line 6890 of file stm32f4xx.h.
| #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
Definition at line 6905 of file stm32f4xx.h.
| #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
Definition at line 6894 of file stm32f4xx.h.
| #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
Definition at line 6906 of file stm32f4xx.h.
| #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
Definition at line 6912 of file stm32f4xx.h.
| #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
Definition at line 6891 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
Definition at line 6907 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
Definition at line 6911 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
Definition at line 6909 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
Definition at line 6908 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
Definition at line 6910 of file stm32f4xx.h.
| #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
Definition at line 6913 of file stm32f4xx.h.
| #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
Definition at line 6904 of file stm32f4xx.h.
| #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
Definition at line 6893 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
Definition at line 6895 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
Definition at line 6897 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
Definition at line 6903 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
Definition at line 6898 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
Definition at line 6902 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
Definition at line 6899 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
Definition at line 6901 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
Definition at line 6900 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
Definition at line 6896 of file stm32f4xx.h.
| #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
Definition at line 6845 of file stm32f4xx.h.
| #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
Definition at line 6842 of file stm32f4xx.h.
| #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
Definition at line 6874 of file stm32f4xx.h.
| #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
Definition at line 6854 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
Definition at line 6858 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
Definition at line 6856 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
Definition at line 6857 of file stm32f4xx.h.
| #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
Definition at line 6875 of file stm32f4xx.h.
| #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
Definition at line 6877 of file stm32f4xx.h.
| #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
Definition at line 6876 of file stm32f4xx.h.
| #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
Definition at line 6853 of file stm32f4xx.h.
| #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
Definition at line 6873 of file stm32f4xx.h.
| #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
Definition at line 6852 of file stm32f4xx.h.
| #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
Definition at line 6880 of file stm32f4xx.h.
| #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
Definition at line 6883 of file stm32f4xx.h.
| #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
Definition at line 6866 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
Definition at line 6871 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
Definition at line 6868 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
Definition at line 6872 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
Definition at line 6867 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
Definition at line 6870 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
Definition at line 6869 of file stm32f4xx.h.
| #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
Definition at line 6879 of file stm32f4xx.h.
| #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
Definition at line 6881 of file stm32f4xx.h.
| #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
Definition at line 6878 of file stm32f4xx.h.
| #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
Definition at line 6885 of file stm32f4xx.h.
| #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
Definition at line 6884 of file stm32f4xx.h.
| #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
Definition at line 6859 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
Definition at line 6865 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
Definition at line 6861 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
Definition at line 6863 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
Definition at line 6860 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
Definition at line 6864 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
Definition at line 6862 of file stm32f4xx.h.
| #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
Definition at line 6886 of file stm32f4xx.h.
| #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
Definition at line 6887 of file stm32f4xx.h.
| #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
Definition at line 6851 of file stm32f4xx.h.
| #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
Definition at line 6882 of file stm32f4xx.h.
| #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
Definition at line 6848 of file stm32f4xx.h.
| #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
Definition at line 6839 of file stm32f4xx.h.
| #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
Definition at line 6641 of file stm32f4xx.h.
| #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
Definition at line 6644 of file stm32f4xx.h.
| #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 6647 of file stm32f4xx.h.
| #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
Definition at line 6656 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
Definition at line 6649 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6650 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6651 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6654 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6653 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6652 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
Definition at line 6655 of file stm32f4xx.h.
| #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 6648 of file stm32f4xx.h.
| #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
Definition at line 6659 of file stm32f4xx.h.
| #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 6662 of file stm32f4xx.h.
| #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
Definition at line 6671 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
Definition at line 6664 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6665 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6666 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6669 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6668 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6667 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
Definition at line 6670 of file stm32f4xx.h.
| #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 6663 of file stm32f4xx.h.
| #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
Definition at line 6674 of file stm32f4xx.h.
| #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 6677 of file stm32f4xx.h.
| #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
Definition at line 6686 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
Definition at line 6679 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6680 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6681 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6684 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6683 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6682 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
Definition at line 6685 of file stm32f4xx.h.
| #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 6678 of file stm32f4xx.h.
| #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
Definition at line 6689 of file stm32f4xx.h.
| #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
Definition at line 6542 of file stm32f4xx.h.
| #define ETH_MACCR_BL |
Definition at line 6543 of file stm32f4xx.h.
| #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
Definition at line 6547 of file stm32f4xx.h.
| #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
Definition at line 6544 of file stm32f4xx.h.
| #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
Definition at line 6546 of file stm32f4xx.h.
| #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
Definition at line 6545 of file stm32f4xx.h.
| #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
Definition at line 6535 of file stm32f4xx.h.
| #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
Definition at line 6548 of file stm32f4xx.h.
| #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
Definition at line 6539 of file stm32f4xx.h.
| #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
Definition at line 6536 of file stm32f4xx.h.
| #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
Definition at line 6526 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
Definition at line 6534 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
Definition at line 6533 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
Definition at line 6532 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
Definition at line 6531 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
Definition at line 6530 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
Definition at line 6529 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
Definition at line 6528 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
Definition at line 6527 of file stm32f4xx.h.
| #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
Definition at line 6540 of file stm32f4xx.h.
| #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
Definition at line 6525 of file stm32f4xx.h.
| #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
Definition at line 6538 of file stm32f4xx.h.
| #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
Definition at line 6541 of file stm32f4xx.h.
| #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
Definition at line 6550 of file stm32f4xx.h.
| #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
Definition at line 6537 of file stm32f4xx.h.
| #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
Definition at line 6549 of file stm32f4xx.h.
| #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
Definition at line 6524 of file stm32f4xx.h.
| #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
Definition at line 6600 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
Definition at line 6592 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
Definition at line 6595 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
Definition at line 6596 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
Definition at line 6594 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
Definition at line 6593 of file stm32f4xx.h.
| #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
Definition at line 6590 of file stm32f4xx.h.
| #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
Definition at line 6598 of file stm32f4xx.h.
| #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
Definition at line 6599 of file stm32f4xx.h.
| #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
Definition at line 6597 of file stm32f4xx.h.
| #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
Definition at line 6591 of file stm32f4xx.h.
| #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
Definition at line 6561 of file stm32f4xx.h.
| #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
Definition at line 6563 of file stm32f4xx.h.
| #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
Definition at line 6564 of file stm32f4xx.h.
| #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
Definition at line 6554 of file stm32f4xx.h.
| #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
Definition at line 6565 of file stm32f4xx.h.
| #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
Definition at line 6562 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
Definition at line 6557 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
Definition at line 6558 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
Definition at line 6559 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
Definition at line 6560 of file stm32f4xx.h.
| #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
Definition at line 6566 of file stm32f4xx.h.
| #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
Definition at line 6553 of file stm32f4xx.h.
| #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
Definition at line 6555 of file stm32f4xx.h.
| #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
Definition at line 6556 of file stm32f4xx.h.
| #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
Definition at line 6569 of file stm32f4xx.h.
| #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
Definition at line 6572 of file stm32f4xx.h.
| #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
Definition at line 6638 of file stm32f4xx.h.
| #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
Definition at line 6637 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
Definition at line 6577 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
Definition at line 6582 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
Definition at line 6580 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
Definition at line 6581 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
Definition at line 6578 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
Definition at line 6579 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
Definition at line 6584 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
Definition at line 6576 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
Definition at line 6583 of file stm32f4xx.h.
| #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
Definition at line 6575 of file stm32f4xx.h.
| #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
Definition at line 6587 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
Definition at line 6622 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
Definition at line 6626 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
Definition at line 6624 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
Definition at line 6627 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
Definition at line 6625 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
Definition at line 6621 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
Definition at line 6623 of file stm32f4xx.h.
| #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
Definition at line 6607 of file stm32f4xx.h.
| #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
Definition at line 6633 of file stm32f4xx.h.
| #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
Definition at line 6631 of file stm32f4xx.h.
| #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
Definition at line 6632 of file stm32f4xx.h.
| #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
Definition at line 6634 of file stm32f4xx.h.
| #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
Definition at line 6630 of file stm32f4xx.h.
| #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
Definition at line 6603 of file stm32f4xx.h.
| #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
Definition at line 6604 of file stm32f4xx.h.
| #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
Definition at line 6701 of file stm32f4xx.h.
| #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
Definition at line 6700 of file stm32f4xx.h.
| #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
Definition at line 6698 of file stm32f4xx.h.
| #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
Definition at line 6696 of file stm32f4xx.h.
| #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
Definition at line 6697 of file stm32f4xx.h.
| #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
Definition at line 6699 of file stm32f4xx.h.
| #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
Definition at line 6736 of file stm32f4xx.h.
| #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
Definition at line 6733 of file stm32f4xx.h.
| #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
Definition at line 6739 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
Definition at line 6715 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
Definition at line 6716 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 6714 of file stm32f4xx.h.
| #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
Definition at line 6705 of file stm32f4xx.h.
| #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
Definition at line 6706 of file stm32f4xx.h.
| #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 6704 of file stm32f4xx.h.
| #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
Definition at line 6730 of file stm32f4xx.h.
| #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
Definition at line 6727 of file stm32f4xx.h.
| #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
Definition at line 6724 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
Definition at line 6719 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
Definition at line 6720 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
Definition at line 6721 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
Definition at line 6710 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
Definition at line 6709 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
Definition at line 6711 of file stm32f4xx.h.
| #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
Definition at line 6764 of file stm32f4xx.h.
| #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
Definition at line 6781 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
Definition at line 6756 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
Definition at line 6746 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
Definition at line 6761 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
Definition at line 6760 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
Definition at line 6757 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
Definition at line 6759 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
Definition at line 6758 of file stm32f4xx.h.
| #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
Definition at line 6767 of file stm32f4xx.h.
| #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
Definition at line 6774 of file stm32f4xx.h.
| #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
Definition at line 6770 of file stm32f4xx.h.
| #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
Definition at line 6771 of file stm32f4xx.h.
| #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
Definition at line 6777 of file stm32f4xx.h.
| #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
Definition at line 6778 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
Definition at line 6752 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
Definition at line 6754 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
Definition at line 6748 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
Definition at line 6749 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
Definition at line 6750 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
Definition at line 6747 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
Definition at line 6791 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
Definition at line 6751 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
Definition at line 6753 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
Definition at line 6790 of file stm32f4xx.h.
| #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
Definition at line 6784 of file stm32f4xx.h.
| #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
Definition at line 6787 of file stm32f4xx.h.
| #define EXTI_EMR_MR0 ((uint32_t)0x00000001) |
Event Mask on line 0
Definition at line 3246 of file stm32f4xx.h.
| #define EXTI_EMR_MR1 ((uint32_t)0x00000002) |
Event Mask on line 1
Definition at line 3247 of file stm32f4xx.h.
| #define EXTI_EMR_MR10 ((uint32_t)0x00000400) |
Event Mask on line 10
Definition at line 3256 of file stm32f4xx.h.
| #define EXTI_EMR_MR11 ((uint32_t)0x00000800) |
Event Mask on line 11
Definition at line 3257 of file stm32f4xx.h.
| #define EXTI_EMR_MR12 ((uint32_t)0x00001000) |
Event Mask on line 12
Definition at line 3258 of file stm32f4xx.h.
| #define EXTI_EMR_MR13 ((uint32_t)0x00002000) |
Event Mask on line 13
Definition at line 3259 of file stm32f4xx.h.
| #define EXTI_EMR_MR14 ((uint32_t)0x00004000) |
Event Mask on line 14
Definition at line 3260 of file stm32f4xx.h.
| #define EXTI_EMR_MR15 ((uint32_t)0x00008000) |
Event Mask on line 15
Definition at line 3261 of file stm32f4xx.h.
| #define EXTI_EMR_MR16 ((uint32_t)0x00010000) |
Event Mask on line 16
Definition at line 3262 of file stm32f4xx.h.
| #define EXTI_EMR_MR17 ((uint32_t)0x00020000) |
Event Mask on line 17
Definition at line 3263 of file stm32f4xx.h.
| #define EXTI_EMR_MR18 ((uint32_t)0x00040000) |
Event Mask on line 18
Definition at line 3264 of file stm32f4xx.h.
| #define EXTI_EMR_MR19 ((uint32_t)0x00080000) |
Event Mask on line 19
Definition at line 3265 of file stm32f4xx.h.
| #define EXTI_EMR_MR2 ((uint32_t)0x00000004) |
Event Mask on line 2
Definition at line 3248 of file stm32f4xx.h.
| #define EXTI_EMR_MR3 ((uint32_t)0x00000008) |
Event Mask on line 3
Definition at line 3249 of file stm32f4xx.h.
| #define EXTI_EMR_MR4 ((uint32_t)0x00000010) |
Event Mask on line 4
Definition at line 3250 of file stm32f4xx.h.
| #define EXTI_EMR_MR5 ((uint32_t)0x00000020) |
Event Mask on line 5
Definition at line 3251 of file stm32f4xx.h.
| #define EXTI_EMR_MR6 ((uint32_t)0x00000040) |
Event Mask on line 6
Definition at line 3252 of file stm32f4xx.h.
| #define EXTI_EMR_MR7 ((uint32_t)0x00000080) |
Event Mask on line 7
Definition at line 3253 of file stm32f4xx.h.
| #define EXTI_EMR_MR8 ((uint32_t)0x00000100) |
Event Mask on line 8
Definition at line 3254 of file stm32f4xx.h.
| #define EXTI_EMR_MR9 ((uint32_t)0x00000200) |
Event Mask on line 9
Definition at line 3255 of file stm32f4xx.h.
| #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
Falling trigger event configuration bit of line 0
Definition at line 3290 of file stm32f4xx.h.
| #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
Falling trigger event configuration bit of line 1
Definition at line 3291 of file stm32f4xx.h.
| #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
Falling trigger event configuration bit of line 10
Definition at line 3300 of file stm32f4xx.h.
| #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
Falling trigger event configuration bit of line 11
Definition at line 3301 of file stm32f4xx.h.
| #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
Falling trigger event configuration bit of line 12
Definition at line 3302 of file stm32f4xx.h.
| #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
Falling trigger event configuration bit of line 13
Definition at line 3303 of file stm32f4xx.h.
| #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
Falling trigger event configuration bit of line 14
Definition at line 3304 of file stm32f4xx.h.
| #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
Falling trigger event configuration bit of line 15
Definition at line 3305 of file stm32f4xx.h.
| #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
Falling trigger event configuration bit of line 16
Definition at line 3306 of file stm32f4xx.h.
| #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
Falling trigger event configuration bit of line 17
Definition at line 3307 of file stm32f4xx.h.
| #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
Falling trigger event configuration bit of line 18
Definition at line 3308 of file stm32f4xx.h.
| #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
Falling trigger event configuration bit of line 19
Definition at line 3309 of file stm32f4xx.h.
| #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
Falling trigger event configuration bit of line 2
Definition at line 3292 of file stm32f4xx.h.
| #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
Falling trigger event configuration bit of line 3
Definition at line 3293 of file stm32f4xx.h.
| #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
Falling trigger event configuration bit of line 4
Definition at line 3294 of file stm32f4xx.h.
| #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
Falling trigger event configuration bit of line 5
Definition at line 3295 of file stm32f4xx.h.
| #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
Falling trigger event configuration bit of line 6
Definition at line 3296 of file stm32f4xx.h.
| #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
Falling trigger event configuration bit of line 7
Definition at line 3297 of file stm32f4xx.h.
| #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
Falling trigger event configuration bit of line 8
Definition at line 3298 of file stm32f4xx.h.
| #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
Falling trigger event configuration bit of line 9
Definition at line 3299 of file stm32f4xx.h.
| #define EXTI_IMR_MR0 ((uint32_t)0x00000001) |
Interrupt Mask on line 0
Definition at line 3224 of file stm32f4xx.h.
| #define EXTI_IMR_MR1 ((uint32_t)0x00000002) |
Interrupt Mask on line 1
Definition at line 3225 of file stm32f4xx.h.
| #define EXTI_IMR_MR10 ((uint32_t)0x00000400) |
Interrupt Mask on line 10
Definition at line 3234 of file stm32f4xx.h.
| #define EXTI_IMR_MR11 ((uint32_t)0x00000800) |
Interrupt Mask on line 11
Definition at line 3235 of file stm32f4xx.h.
| #define EXTI_IMR_MR12 ((uint32_t)0x00001000) |
Interrupt Mask on line 12
Definition at line 3236 of file stm32f4xx.h.
| #define EXTI_IMR_MR13 ((uint32_t)0x00002000) |
Interrupt Mask on line 13
Definition at line 3237 of file stm32f4xx.h.
| #define EXTI_IMR_MR14 ((uint32_t)0x00004000) |
Interrupt Mask on line 14
Definition at line 3238 of file stm32f4xx.h.
| #define EXTI_IMR_MR15 ((uint32_t)0x00008000) |
Interrupt Mask on line 15
Definition at line 3239 of file stm32f4xx.h.
| #define EXTI_IMR_MR16 ((uint32_t)0x00010000) |
Interrupt Mask on line 16
Definition at line 3240 of file stm32f4xx.h.
| #define EXTI_IMR_MR17 ((uint32_t)0x00020000) |
Interrupt Mask on line 17
Definition at line 3241 of file stm32f4xx.h.
| #define EXTI_IMR_MR18 ((uint32_t)0x00040000) |
Interrupt Mask on line 18
Definition at line 3242 of file stm32f4xx.h.
| #define EXTI_IMR_MR19 ((uint32_t)0x00080000) |
Interrupt Mask on line 19
Definition at line 3243 of file stm32f4xx.h.
| #define EXTI_IMR_MR2 ((uint32_t)0x00000004) |
Interrupt Mask on line 2
Definition at line 3226 of file stm32f4xx.h.
| #define EXTI_IMR_MR3 ((uint32_t)0x00000008) |
Interrupt Mask on line 3
Definition at line 3227 of file stm32f4xx.h.
| #define EXTI_IMR_MR4 ((uint32_t)0x00000010) |
Interrupt Mask on line 4
Definition at line 3228 of file stm32f4xx.h.
| #define EXTI_IMR_MR5 ((uint32_t)0x00000020) |
Interrupt Mask on line 5
Definition at line 3229 of file stm32f4xx.h.
| #define EXTI_IMR_MR6 ((uint32_t)0x00000040) |
Interrupt Mask on line 6
Definition at line 3230 of file stm32f4xx.h.
| #define EXTI_IMR_MR7 ((uint32_t)0x00000080) |
Interrupt Mask on line 7
Definition at line 3231 of file stm32f4xx.h.
| #define EXTI_IMR_MR8 ((uint32_t)0x00000100) |
Interrupt Mask on line 8
Definition at line 3232 of file stm32f4xx.h.
| #define EXTI_IMR_MR9 ((uint32_t)0x00000200) |
Interrupt Mask on line 9
Definition at line 3233 of file stm32f4xx.h.
| #define EXTI_PR_PR0 ((uint32_t)0x00000001) |
Pending bit for line 0
Definition at line 3334 of file stm32f4xx.h.
| #define EXTI_PR_PR1 ((uint32_t)0x00000002) |
Pending bit for line 1
Definition at line 3335 of file stm32f4xx.h.
| #define EXTI_PR_PR10 ((uint32_t)0x00000400) |
Pending bit for line 10
Definition at line 3344 of file stm32f4xx.h.
| #define EXTI_PR_PR11 ((uint32_t)0x00000800) |
Pending bit for line 11
Definition at line 3345 of file stm32f4xx.h.
| #define EXTI_PR_PR12 ((uint32_t)0x00001000) |
Pending bit for line 12
Definition at line 3346 of file stm32f4xx.h.
| #define EXTI_PR_PR13 ((uint32_t)0x00002000) |
Pending bit for line 13
Definition at line 3347 of file stm32f4xx.h.
| #define EXTI_PR_PR14 ((uint32_t)0x00004000) |
Pending bit for line 14
Definition at line 3348 of file stm32f4xx.h.
| #define EXTI_PR_PR15 ((uint32_t)0x00008000) |
Pending bit for line 15
Definition at line 3349 of file stm32f4xx.h.
| #define EXTI_PR_PR16 ((uint32_t)0x00010000) |
Pending bit for line 16
Definition at line 3350 of file stm32f4xx.h.
| #define EXTI_PR_PR17 ((uint32_t)0x00020000) |
Pending bit for line 17
Definition at line 3351 of file stm32f4xx.h.
| #define EXTI_PR_PR18 ((uint32_t)0x00040000) |
Pending bit for line 18
Definition at line 3352 of file stm32f4xx.h.
| #define EXTI_PR_PR19 ((uint32_t)0x00080000) |
Pending bit for line 19
Definition at line 3353 of file stm32f4xx.h.
| #define EXTI_PR_PR2 ((uint32_t)0x00000004) |
Pending bit for line 2
Definition at line 3336 of file stm32f4xx.h.
| #define EXTI_PR_PR3 ((uint32_t)0x00000008) |
Pending bit for line 3
Definition at line 3337 of file stm32f4xx.h.
| #define EXTI_PR_PR4 ((uint32_t)0x00000010) |
Pending bit for line 4
Definition at line 3338 of file stm32f4xx.h.
| #define EXTI_PR_PR5 ((uint32_t)0x00000020) |
Pending bit for line 5
Definition at line 3339 of file stm32f4xx.h.
| #define EXTI_PR_PR6 ((uint32_t)0x00000040) |
Pending bit for line 6
Definition at line 3340 of file stm32f4xx.h.
| #define EXTI_PR_PR7 ((uint32_t)0x00000080) |
Pending bit for line 7
Definition at line 3341 of file stm32f4xx.h.
| #define EXTI_PR_PR8 ((uint32_t)0x00000100) |
Pending bit for line 8
Definition at line 3342 of file stm32f4xx.h.
| #define EXTI_PR_PR9 ((uint32_t)0x00000200) |
Pending bit for line 9
Definition at line 3343 of file stm32f4xx.h.
| #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
Rising trigger event configuration bit of line 0
Definition at line 3268 of file stm32f4xx.h.
| #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
Rising trigger event configuration bit of line 1
Definition at line 3269 of file stm32f4xx.h.
| #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
Rising trigger event configuration bit of line 10
Definition at line 3278 of file stm32f4xx.h.
| #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
Rising trigger event configuration bit of line 11
Definition at line 3279 of file stm32f4xx.h.
| #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
Rising trigger event configuration bit of line 12
Definition at line 3280 of file stm32f4xx.h.
| #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
Rising trigger event configuration bit of line 13
Definition at line 3281 of file stm32f4xx.h.
| #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
Rising trigger event configuration bit of line 14
Definition at line 3282 of file stm32f4xx.h.
| #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
Rising trigger event configuration bit of line 15
Definition at line 3283 of file stm32f4xx.h.
| #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
Rising trigger event configuration bit of line 16
Definition at line 3284 of file stm32f4xx.h.
| #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
Rising trigger event configuration bit of line 17
Definition at line 3285 of file stm32f4xx.h.
| #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
Rising trigger event configuration bit of line 18
Definition at line 3286 of file stm32f4xx.h.
| #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
Rising trigger event configuration bit of line 19
Definition at line 3287 of file stm32f4xx.h.
| #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
Rising trigger event configuration bit of line 2
Definition at line 3270 of file stm32f4xx.h.
| #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
Rising trigger event configuration bit of line 3
Definition at line 3271 of file stm32f4xx.h.
| #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
Rising trigger event configuration bit of line 4
Definition at line 3272 of file stm32f4xx.h.
| #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
Rising trigger event configuration bit of line 5
Definition at line 3273 of file stm32f4xx.h.
| #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
Rising trigger event configuration bit of line 6
Definition at line 3274 of file stm32f4xx.h.
| #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
Rising trigger event configuration bit of line 7
Definition at line 3275 of file stm32f4xx.h.
| #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
Rising trigger event configuration bit of line 8
Definition at line 3276 of file stm32f4xx.h.
| #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
Rising trigger event configuration bit of line 9
Definition at line 3277 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
Software Interrupt on line 0
Definition at line 3312 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
Software Interrupt on line 1
Definition at line 3313 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
Software Interrupt on line 10
Definition at line 3322 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
Software Interrupt on line 11
Definition at line 3323 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
Software Interrupt on line 12
Definition at line 3324 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
Software Interrupt on line 13
Definition at line 3325 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
Software Interrupt on line 14
Definition at line 3326 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
Software Interrupt on line 15
Definition at line 3327 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
Software Interrupt on line 16
Definition at line 3328 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
Software Interrupt on line 17
Definition at line 3329 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
Software Interrupt on line 18
Definition at line 3330 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
Software Interrupt on line 19
Definition at line 3331 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
Software Interrupt on line 2
Definition at line 3314 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
Software Interrupt on line 3
Definition at line 3315 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
Software Interrupt on line 4
Definition at line 3316 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
Software Interrupt on line 5
Definition at line 3317 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
Software Interrupt on line 6
Definition at line 3318 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
Software Interrupt on line 7
Definition at line 3319 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
Software Interrupt on line 8
Definition at line 3320 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
Software Interrupt on line 9
Definition at line 3321 of file stm32f4xx.h.
| #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
Definition at line 3376 of file stm32f4xx.h.
| #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
Definition at line 3377 of file stm32f4xx.h.
| #define FLASH_ACR_DCEN ((uint32_t)0x00000400) |
Definition at line 3373 of file stm32f4xx.h.
| #define FLASH_ACR_DCRST ((uint32_t)0x00001000) |
Definition at line 3375 of file stm32f4xx.h.
| #define FLASH_ACR_ICEN ((uint32_t)0x00000200) |
Definition at line 3372 of file stm32f4xx.h.
| #define FLASH_ACR_ICRST ((uint32_t)0x00000800) |
Definition at line 3374 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
Definition at line 3361 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
Definition at line 3362 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
Definition at line 3363 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
Definition at line 3364 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
Definition at line 3365 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
Definition at line 3366 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
Definition at line 3367 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
Definition at line 3368 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
Definition at line 3369 of file stm32f4xx.h.
| #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
Definition at line 3371 of file stm32f4xx.h.
| #define FLASH_CR_EOPIE ((uint32_t)0x01000000) |
Definition at line 3399 of file stm32f4xx.h.
| #define FLASH_CR_LOCK ((uint32_t)0x80000000) |
Definition at line 3400 of file stm32f4xx.h.
| #define FLASH_CR_MER ((uint32_t)0x00000004) |
Definition at line 3391 of file stm32f4xx.h.
| #define FLASH_CR_PG ((uint32_t)0x00000001) |
Definition at line 3389 of file stm32f4xx.h.
| #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
Definition at line 3396 of file stm32f4xx.h.
| #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
Definition at line 3397 of file stm32f4xx.h.
| #define FLASH_CR_SER ((uint32_t)0x00000002) |
Definition at line 3390 of file stm32f4xx.h.
| #define FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
Definition at line 3392 of file stm32f4xx.h.
| #define FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
Definition at line 3393 of file stm32f4xx.h.
| #define FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
Definition at line 3394 of file stm32f4xx.h.
| #define FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
Definition at line 3395 of file stm32f4xx.h.
| #define FLASH_CR_STRT ((uint32_t)0x00010000) |
Definition at line 3398 of file stm32f4xx.h.
| #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
Definition at line 3407 of file stm32f4xx.h.
| #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
Definition at line 3405 of file stm32f4xx.h.
| #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
Definition at line 3406 of file stm32f4xx.h.
| #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
Definition at line 3410 of file stm32f4xx.h.
| #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
Definition at line 3409 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
Definition at line 3419 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
Definition at line 3420 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
Definition at line 3429 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
Definition at line 3430 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
Definition at line 3421 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
Definition at line 3422 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
Definition at line 3423 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
Definition at line 3424 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
Definition at line 3425 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
Definition at line 3426 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
Definition at line 3427 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
Definition at line 3428 of file stm32f4xx.h.
| #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
Definition at line 3403 of file stm32f4xx.h.
| #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
Definition at line 3404 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
Definition at line 3411 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
Definition at line 3412 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
Definition at line 3413 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
Definition at line 3414 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
Definition at line 3415 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
Definition at line 3416 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
Definition at line 3417 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
Definition at line 3418 of file stm32f4xx.h.
| #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
Definition at line 3408 of file stm32f4xx.h.
| #define FLASH_SR_BSY ((uint32_t)0x00010000) |
Definition at line 3386 of file stm32f4xx.h.
| #define FLASH_SR_EOP ((uint32_t)0x00000001) |
Definition at line 3380 of file stm32f4xx.h.
| #define FLASH_SR_PGAERR ((uint32_t)0x00000020) |
Definition at line 3383 of file stm32f4xx.h.
| #define FLASH_SR_PGPERR ((uint32_t)0x00000040) |
Definition at line 3384 of file stm32f4xx.h.
| #define FLASH_SR_PGSERR ((uint32_t)0x00000080) |
Definition at line 3385 of file stm32f4xx.h.
| #define FLASH_SR_SOP ((uint32_t)0x00000002) |
Definition at line 3381 of file stm32f4xx.h.
| #define FLASH_SR_WRPERR ((uint32_t)0x00000010) |
Definition at line 3382 of file stm32f4xx.h.
| #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
Asynchronous wait
Definition at line 3457 of file stm32f4xx.h.
| #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
Burst enable bit
Definition at line 3450 of file stm32f4xx.h.
| #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
Write burst enable
Definition at line 3458 of file stm32f4xx.h.
| #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
Extended mode enable
Definition at line 3456 of file stm32f4xx.h.
| #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
Flash access enable
Definition at line 3449 of file stm32f4xx.h.
| #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
Memory bank enable bit
Definition at line 3438 of file stm32f4xx.h.
| #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
MTYP[1:0] bits (Memory type)
Definition at line 3441 of file stm32f4xx.h.
| #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 3442 of file stm32f4xx.h.
| #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 3443 of file stm32f4xx.h.
| #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
Address/data multiplexing enable bit
Definition at line 3439 of file stm32f4xx.h.
| #define FSMC_BCR1_MWID ((uint32_t)0x00000030) |
MWID[1:0] bits (Memory data bus width)
Definition at line 3445 of file stm32f4xx.h.
| #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3446 of file stm32f4xx.h.
| #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3447 of file stm32f4xx.h.
| #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
Wait timing configuration
Definition at line 3453 of file stm32f4xx.h.
| #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
Wait enable bit
Definition at line 3455 of file stm32f4xx.h.
| #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
Wait signal polarity bit
Definition at line 3451 of file stm32f4xx.h.
| #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
Wrapped burst mode support
Definition at line 3452 of file stm32f4xx.h.
| #define FSMC_BCR1_WREN ((uint32_t)0x00001000) |
Write enable bit
Definition at line 3454 of file stm32f4xx.h.
| #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
Asynchronous wait
Definition at line 3480 of file stm32f4xx.h.
| #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
Burst enable bit
Definition at line 3473 of file stm32f4xx.h.
| #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
Write burst enable
Definition at line 3481 of file stm32f4xx.h.
| #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
Extended mode enable
Definition at line 3479 of file stm32f4xx.h.
| #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
Flash access enable
Definition at line 3472 of file stm32f4xx.h.
| #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
Memory bank enable bit
Definition at line 3461 of file stm32f4xx.h.
| #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
MTYP[1:0] bits (Memory type)
Definition at line 3464 of file stm32f4xx.h.
| #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 3465 of file stm32f4xx.h.
| #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 3466 of file stm32f4xx.h.
| #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
Address/data multiplexing enable bit
Definition at line 3462 of file stm32f4xx.h.
| #define FSMC_BCR2_MWID ((uint32_t)0x00000030) |
MWID[1:0] bits (Memory data bus width)
Definition at line 3468 of file stm32f4xx.h.
| #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3469 of file stm32f4xx.h.
| #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3470 of file stm32f4xx.h.
| #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
Wait timing configuration
Definition at line 3476 of file stm32f4xx.h.
| #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
Wait enable bit
Definition at line 3478 of file stm32f4xx.h.
| #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
Wait signal polarity bit
Definition at line 3474 of file stm32f4xx.h.
| #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
Wrapped burst mode support
Definition at line 3475 of file stm32f4xx.h.
| #define FSMC_BCR2_WREN ((uint32_t)0x00001000) |
Write enable bit
Definition at line 3477 of file stm32f4xx.h.
| #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
Asynchronous wait
Definition at line 3503 of file stm32f4xx.h.
| #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
Burst enable bit
Definition at line 3496 of file stm32f4xx.h.
| #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
Write burst enable
Definition at line 3504 of file stm32f4xx.h.
| #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
Extended mode enable
Definition at line 3502 of file stm32f4xx.h.
| #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
Flash access enable
Definition at line 3495 of file stm32f4xx.h.
| #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
Memory bank enable bit
Definition at line 3484 of file stm32f4xx.h.
| #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
MTYP[1:0] bits (Memory type)
Definition at line 3487 of file stm32f4xx.h.
| #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 3488 of file stm32f4xx.h.
| #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 3489 of file stm32f4xx.h.
| #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
Address/data multiplexing enable bit
Definition at line 3485 of file stm32f4xx.h.
| #define FSMC_BCR3_MWID ((uint32_t)0x00000030) |
MWID[1:0] bits (Memory data bus width)
Definition at line 3491 of file stm32f4xx.h.
| #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3492 of file stm32f4xx.h.
| #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3493 of file stm32f4xx.h.
| #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
Wait timing configuration
Definition at line 3499 of file stm32f4xx.h.
| #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
Wait enable bit
Definition at line 3501 of file stm32f4xx.h.
| #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
Wait signal polarity bit.
Definition at line 3497 of file stm32f4xx.h.
| #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
Wrapped burst mode support
Definition at line 3498 of file stm32f4xx.h.
| #define FSMC_BCR3_WREN ((uint32_t)0x00001000) |
Write enable bit
Definition at line 3500 of file stm32f4xx.h.
| #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
Asynchronous wait
Definition at line 3526 of file stm32f4xx.h.
| #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
Burst enable bit
Definition at line 3519 of file stm32f4xx.h.
| #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
Write burst enable
Definition at line 3527 of file stm32f4xx.h.
| #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
Extended mode enable
Definition at line 3525 of file stm32f4xx.h.
| #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
Flash access enable
Definition at line 3518 of file stm32f4xx.h.
| #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
Memory bank enable bit
Definition at line 3507 of file stm32f4xx.h.
| #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
MTYP[1:0] bits (Memory type)
Definition at line 3510 of file stm32f4xx.h.
| #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 3511 of file stm32f4xx.h.
| #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 3512 of file stm32f4xx.h.
| #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
Address/data multiplexing enable bit
Definition at line 3508 of file stm32f4xx.h.
| #define FSMC_BCR4_MWID ((uint32_t)0x00000030) |
MWID[1:0] bits (Memory data bus width)
Definition at line 3514 of file stm32f4xx.h.
| #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3515 of file stm32f4xx.h.
| #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3516 of file stm32f4xx.h.
| #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
Wait timing configuration
Definition at line 3522 of file stm32f4xx.h.
| #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
Wait enable bit
Definition at line 3524 of file stm32f4xx.h.
| #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
Wait signal polarity bit
Definition at line 3520 of file stm32f4xx.h.
| #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
Wrapped burst mode support
Definition at line 3521 of file stm32f4xx.h.
| #define FSMC_BCR4_WREN ((uint32_t)0x00001000) |
Write enable bit
Definition at line 3523 of file stm32f4xx.h.
| #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3566 of file stm32f4xx.h.
| #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3567 of file stm32f4xx.h.
| #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3568 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3536 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3537 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3538 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3539 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3540 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3530 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3531 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3532 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3533 of file stm32f4xx.h.
| #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3534 of file stm32f4xx.h.
| #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3548 of file stm32f4xx.h.
| #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 3549 of file stm32f4xx.h.
| #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 3550 of file stm32f4xx.h.
| #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 3551 of file stm32f4xx.h.
| #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 3552 of file stm32f4xx.h.
| #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3554 of file stm32f4xx.h.
| #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3555 of file stm32f4xx.h.
| #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3556 of file stm32f4xx.h.
| #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3557 of file stm32f4xx.h.
| #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3558 of file stm32f4xx.h.
| #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3542 of file stm32f4xx.h.
| #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3543 of file stm32f4xx.h.
| #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3544 of file stm32f4xx.h.
| #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3545 of file stm32f4xx.h.
| #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3546 of file stm32f4xx.h.
| #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3560 of file stm32f4xx.h.
| #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3561 of file stm32f4xx.h.
| #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3562 of file stm32f4xx.h.
| #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3563 of file stm32f4xx.h.
| #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3564 of file stm32f4xx.h.
| #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3607 of file stm32f4xx.h.
| #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3608 of file stm32f4xx.h.
| #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3609 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3577 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3578 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3579 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3580 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3581 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3571 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3572 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3573 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3574 of file stm32f4xx.h.
| #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3575 of file stm32f4xx.h.
| #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3589 of file stm32f4xx.h.
| #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 3590 of file stm32f4xx.h.
| #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 3591 of file stm32f4xx.h.
| #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 3592 of file stm32f4xx.h.
| #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 3593 of file stm32f4xx.h.
| #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3595 of file stm32f4xx.h.
| #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3596 of file stm32f4xx.h.
| #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3597 of file stm32f4xx.h.
| #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3598 of file stm32f4xx.h.
| #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3599 of file stm32f4xx.h.
| #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3583 of file stm32f4xx.h.
| #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3584 of file stm32f4xx.h.
| #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3585 of file stm32f4xx.h.
| #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3586 of file stm32f4xx.h.
| #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3587 of file stm32f4xx.h.
| #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3601 of file stm32f4xx.h.
| #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3602 of file stm32f4xx.h.
| #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3603 of file stm32f4xx.h.
| #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3604 of file stm32f4xx.h.
| #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3605 of file stm32f4xx.h.
| #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3648 of file stm32f4xx.h.
| #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3649 of file stm32f4xx.h.
| #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3650 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3618 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3619 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3620 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3621 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3622 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3612 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3613 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3614 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3615 of file stm32f4xx.h.
| #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3616 of file stm32f4xx.h.
| #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3630 of file stm32f4xx.h.
| #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 3631 of file stm32f4xx.h.
| #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 3632 of file stm32f4xx.h.
| #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 3633 of file stm32f4xx.h.
| #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 3634 of file stm32f4xx.h.
| #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3636 of file stm32f4xx.h.
| #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3637 of file stm32f4xx.h.
| #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3638 of file stm32f4xx.h.
| #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3639 of file stm32f4xx.h.
| #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3640 of file stm32f4xx.h.
| #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3624 of file stm32f4xx.h.
| #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3625 of file stm32f4xx.h.
| #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3626 of file stm32f4xx.h.
| #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3627 of file stm32f4xx.h.
| #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3628 of file stm32f4xx.h.
| #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3642 of file stm32f4xx.h.
| #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3643 of file stm32f4xx.h.
| #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3644 of file stm32f4xx.h.
| #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3645 of file stm32f4xx.h.
| #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3646 of file stm32f4xx.h.
| #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3689 of file stm32f4xx.h.
| #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3690 of file stm32f4xx.h.
| #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3691 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3659 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3660 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3661 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3662 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3663 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3653 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3654 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3655 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3656 of file stm32f4xx.h.
| #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3657 of file stm32f4xx.h.
| #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3671 of file stm32f4xx.h.
| #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 3672 of file stm32f4xx.h.
| #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 3673 of file stm32f4xx.h.
| #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 3674 of file stm32f4xx.h.
| #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 3675 of file stm32f4xx.h.
| #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3677 of file stm32f4xx.h.
| #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3678 of file stm32f4xx.h.
| #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3679 of file stm32f4xx.h.
| #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3680 of file stm32f4xx.h.
| #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3681 of file stm32f4xx.h.
| #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3665 of file stm32f4xx.h.
| #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3666 of file stm32f4xx.h.
| #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3667 of file stm32f4xx.h.
| #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3668 of file stm32f4xx.h.
| #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3669 of file stm32f4xx.h.
| #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3683 of file stm32f4xx.h.
| #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3684 of file stm32f4xx.h.
| #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3685 of file stm32f4xx.h.
| #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3686 of file stm32f4xx.h.
| #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3687 of file stm32f4xx.h.
| #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3724 of file stm32f4xx.h.
| #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3725 of file stm32f4xx.h.
| #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3726 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3700 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3701 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3702 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3703 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3704 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3694 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3695 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3696 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3697 of file stm32f4xx.h.
| #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3698 of file stm32f4xx.h.
| #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3712 of file stm32f4xx.h.
| #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3713 of file stm32f4xx.h.
| #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3714 of file stm32f4xx.h.
| #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3715 of file stm32f4xx.h.
| #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3716 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3706 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3707 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3708 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3709 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3710 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3718 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3719 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3720 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3721 of file stm32f4xx.h.
| #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3722 of file stm32f4xx.h.
| #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3759 of file stm32f4xx.h.
| #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3760 of file stm32f4xx.h.
| #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3761 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3735 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3736 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3737 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3738 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3739 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3729 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3730 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3731 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3732 of file stm32f4xx.h.
| #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3733 of file stm32f4xx.h.
| #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3747 of file stm32f4xx.h.
| #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3748 of file stm32f4xx.h.
| #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3749 of file stm32f4xx.h.
| #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3750 of file stm32f4xx.h.
| #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3751 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3741 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3742 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3743 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3744 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3745 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3753 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3754 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3755 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3756 of file stm32f4xx.h.
| #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3757 of file stm32f4xx.h.
| #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3794 of file stm32f4xx.h.
| #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3795 of file stm32f4xx.h.
| #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3796 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3770 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3771 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3772 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3773 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3774 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3764 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3765 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3766 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3767 of file stm32f4xx.h.
| #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3768 of file stm32f4xx.h.
| #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3782 of file stm32f4xx.h.
| #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3783 of file stm32f4xx.h.
| #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3784 of file stm32f4xx.h.
| #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3785 of file stm32f4xx.h.
| #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3786 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3776 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3777 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3778 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3779 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3780 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3788 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3789 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3790 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3791 of file stm32f4xx.h.
| #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3792 of file stm32f4xx.h.
| #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
ACCMOD[1:0] bits (Access mode)
Definition at line 3829 of file stm32f4xx.h.
| #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 3830 of file stm32f4xx.h.
| #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 3831 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3805 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3806 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3807 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 3808 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 3809 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3799 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3800 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3801 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3802 of file stm32f4xx.h.
| #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3803 of file stm32f4xx.h.
| #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3817 of file stm32f4xx.h.
| #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 3818 of file stm32f4xx.h.
| #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 3819 of file stm32f4xx.h.
| #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 3820 of file stm32f4xx.h.
| #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 3821 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3811 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3812 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3813 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3814 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3815 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
DATLA[3:0] bits (Data latency)
Definition at line 3823 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3824 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3825 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3826 of file stm32f4xx.h.
| #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3827 of file stm32f4xx.h.
| #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
ECC result
Definition at line 4232 of file stm32f4xx.h.
| #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
ECC result
Definition at line 4235 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) |
ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)
Definition at line 4098 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4099 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4100 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4101 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4102 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4103 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4104 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4105 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4106 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) |
ATTHOLD2[7:0] bits (Attribute memory 2 hold time)
Definition at line 4088 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4089 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4090 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4091 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4092 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4093 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4094 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4095 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4096 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) |
ATTSET2[7:0] bits (Attribute memory 2 setup time)
Definition at line 4068 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4069 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4070 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 4071 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 4072 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 4073 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 4074 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 4075 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 4076 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) |
ATTWAIT2[7:0] bits (Attribute memory 2 wait time)
Definition at line 4078 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4079 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4080 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4081 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4082 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4083 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4084 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4085 of file stm32f4xx.h.
| #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4086 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) |
ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)
Definition at line 4139 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4140 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4141 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4142 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4143 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4144 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4145 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4146 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4147 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) |
ATTHOLD3[7:0] bits (Attribute memory 3 hold time)
Definition at line 4129 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4130 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4131 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4132 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4133 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4134 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4135 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4136 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4137 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) |
ATTSET3[7:0] bits (Attribute memory 3 setup time)
Definition at line 4109 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4110 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4111 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 4112 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 4113 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 4114 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 4115 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 4116 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 4117 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) |
ATTWAIT3[7:0] bits (Attribute memory 3 wait time)
Definition at line 4119 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4120 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4121 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4122 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4123 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4124 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4125 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4126 of file stm32f4xx.h.
| #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4127 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) |
ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)
Definition at line 4180 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4181 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4182 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4183 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4184 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4185 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4186 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4187 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4188 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) |
ATTHOLD4[7:0] bits (Attribute memory 4 hold time)
Definition at line 4170 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4171 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4172 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4173 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4174 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4175 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4176 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4177 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4178 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) |
ATTSET4[7:0] bits (Attribute memory 4 setup time)
Definition at line 4150 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4151 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4152 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 4153 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 4154 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 4155 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 4156 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 4157 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 4158 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) |
ATTWAIT4[7:0] bits (Attribute memory 4 wait time)
Definition at line 4160 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4161 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4162 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4163 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4164 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4165 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4166 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4167 of file stm32f4xx.h.
| #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4168 of file stm32f4xx.h.
| #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) |
ECC computation logic enable bit
Definition at line 3842 of file stm32f4xx.h.
| #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) |
ECCPS[1:0] bits (ECC page size)
Definition at line 3856 of file stm32f4xx.h.
| #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) |
Bit 0
Definition at line 3857 of file stm32f4xx.h.
| #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) |
Bit 1
Definition at line 3858 of file stm32f4xx.h.
| #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) |
Bit 2
Definition at line 3859 of file stm32f4xx.h.
| #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) |
PC Card/NAND Flash memory bank enable bit
Definition at line 3835 of file stm32f4xx.h.
| #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) |
Memory type
Definition at line 3836 of file stm32f4xx.h.
| #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) |
Wait feature enable bit
Definition at line 3834 of file stm32f4xx.h.
| #define FSMC_PCR2_PWID ((uint32_t)0x00000030) |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3838 of file stm32f4xx.h.
| #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3839 of file stm32f4xx.h.
| #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3840 of file stm32f4xx.h.
| #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3850 of file stm32f4xx.h.
| #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 3851 of file stm32f4xx.h.
| #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 3852 of file stm32f4xx.h.
| #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 3853 of file stm32f4xx.h.
| #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) |
Bit 3
Definition at line 3854 of file stm32f4xx.h.
| #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3844 of file stm32f4xx.h.
| #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 3845 of file stm32f4xx.h.
| #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 3846 of file stm32f4xx.h.
| #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 3847 of file stm32f4xx.h.
| #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) |
Bit 3
Definition at line 3848 of file stm32f4xx.h.
| #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) |
ECC computation logic enable bit
Definition at line 3870 of file stm32f4xx.h.
| #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) |
ECCPS[2:0] bits (ECC page size)
Definition at line 3884 of file stm32f4xx.h.
| #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) |
Bit 0
Definition at line 3885 of file stm32f4xx.h.
| #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) |
Bit 1
Definition at line 3886 of file stm32f4xx.h.
| #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) |
Bit 2
Definition at line 3887 of file stm32f4xx.h.
| #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) |
PC Card/NAND Flash memory bank enable bit
Definition at line 3863 of file stm32f4xx.h.
| #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) |
Memory type
Definition at line 3864 of file stm32f4xx.h.
| #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) |
Wait feature enable bit
Definition at line 3862 of file stm32f4xx.h.
| #define FSMC_PCR3_PWID ((uint32_t)0x00000030) |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3866 of file stm32f4xx.h.
| #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3867 of file stm32f4xx.h.
| #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3868 of file stm32f4xx.h.
| #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3878 of file stm32f4xx.h.
| #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 3879 of file stm32f4xx.h.
| #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 3880 of file stm32f4xx.h.
| #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 3881 of file stm32f4xx.h.
| #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) |
Bit 3
Definition at line 3882 of file stm32f4xx.h.
| #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3872 of file stm32f4xx.h.
| #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 3873 of file stm32f4xx.h.
| #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 3874 of file stm32f4xx.h.
| #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 3875 of file stm32f4xx.h.
| #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) |
Bit 3
Definition at line 3876 of file stm32f4xx.h.
| #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) |
ECC computation logic enable bit
Definition at line 3898 of file stm32f4xx.h.
| #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) |
ECCPS[2:0] bits (ECC page size)
Definition at line 3912 of file stm32f4xx.h.
| #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) |
Bit 0
Definition at line 3913 of file stm32f4xx.h.
| #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) |
Bit 1
Definition at line 3914 of file stm32f4xx.h.
| #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) |
Bit 2
Definition at line 3915 of file stm32f4xx.h.
| #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) |
PC Card/NAND Flash memory bank enable bit
Definition at line 3891 of file stm32f4xx.h.
| #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) |
Memory type
Definition at line 3892 of file stm32f4xx.h.
| #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) |
Wait feature enable bit
Definition at line 3890 of file stm32f4xx.h.
| #define FSMC_PCR4_PWID ((uint32_t)0x00000030) |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3894 of file stm32f4xx.h.
| #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 3895 of file stm32f4xx.h.
| #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 3896 of file stm32f4xx.h.
| #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3906 of file stm32f4xx.h.
| #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 3907 of file stm32f4xx.h.
| #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 3908 of file stm32f4xx.h.
| #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 3909 of file stm32f4xx.h.
| #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) |
Bit 3
Definition at line 3910 of file stm32f4xx.h.
| #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3900 of file stm32f4xx.h.
| #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 3901 of file stm32f4xx.h.
| #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 3902 of file stm32f4xx.h.
| #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 3903 of file stm32f4xx.h.
| #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) |
Bit 3
Definition at line 3904 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
IOHIZ4[7:0] bits (I/O 4 databus HiZ time)
Definition at line 4221 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4222 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4223 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4224 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4225 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4226 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4227 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4228 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4229 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
IOHOLD4[7:0] bits (I/O 4 hold time)
Definition at line 4211 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4212 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4213 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4214 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4215 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4216 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4217 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4218 of file stm32f4xx.h.
| #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4219 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
IOSET4[7:0] bits (I/O 4 setup time)
Definition at line 4191 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4192 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4193 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 4194 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 4195 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 4196 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 4197 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 4198 of file stm32f4xx.h.
| #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 4199 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
IOWAIT4[7:0] bits (I/O 4 wait time)
Definition at line 4201 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4202 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4203 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4204 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4205 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4206 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4207 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4208 of file stm32f4xx.h.
| #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4209 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) |
MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)
Definition at line 3975 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 3976 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 3977 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 3978 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 3979 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 3980 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 3981 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 3982 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 3983 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) |
MEMHOLD2[7:0] bits (Common memory 2 hold time)
Definition at line 3965 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 3966 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 3967 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 3968 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 3969 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 3970 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 3971 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 3972 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 3973 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) |
MEMSET2[7:0] bits (Common memory 2 setup time)
Definition at line 3945 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3946 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3947 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3948 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3949 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 3950 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 3951 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 3952 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 3953 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) |
MEMWAIT2[7:0] bits (Common memory 2 wait time)
Definition at line 3955 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3956 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3957 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3958 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 3959 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 3960 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 3961 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 3962 of file stm32f4xx.h.
| #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 3963 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) |
MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)
Definition at line 4016 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4017 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4018 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4019 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4020 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4021 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4022 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4023 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4024 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) |
MEMHOLD3[7:0] bits (Common memory 3 hold time)
Definition at line 4006 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4007 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4008 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4009 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4010 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4011 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4012 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4013 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4014 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) |
MEMSET3[7:0] bits (Common memory 3 setup time)
Definition at line 3986 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 3987 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 3988 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 3989 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 3990 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 3991 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 3992 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 3993 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 3994 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) |
MEMWAIT3[7:0] bits (Common memory 3 wait time)
Definition at line 3996 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 3997 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 3998 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 3999 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4000 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4001 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4002 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4003 of file stm32f4xx.h.
| #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4004 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) |
MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)
Definition at line 4057 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4058 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4059 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4060 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4061 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) |
Bit 4
Definition at line 4062 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) |
Bit 5
Definition at line 4063 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) |
Bit 6
Definition at line 4064 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) |
Bit 7
Definition at line 4065 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) |
MEMHOLD4[7:0] bits (Common memory 4 hold time)
Definition at line 4047 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 4048 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 4049 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 4050 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 4051 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) |
Bit 4
Definition at line 4052 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) |
Bit 5
Definition at line 4053 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) |
Bit 6
Definition at line 4054 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) |
Bit 7
Definition at line 4055 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) |
MEMSET4[7:0] bits (Common memory 4 setup time)
Definition at line 4027 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4028 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4029 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 4030 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 4031 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 4032 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 4033 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 4034 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 4035 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) |
MEMWAIT4[7:0] bits (Common memory 4 wait time)
Definition at line 4037 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4038 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4039 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4040 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4041 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 4042 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 4043 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 4044 of file stm32f4xx.h.
| #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) |
Bit 7
Definition at line 4045 of file stm32f4xx.h.
| #define FSMC_SR2_FEMPT ((uint8_t)0x40) |
FIFO empty
Definition at line 3924 of file stm32f4xx.h.
| #define FSMC_SR2_IFEN ((uint8_t)0x20) |
Interrupt Falling Edge detection Enable bit
Definition at line 3923 of file stm32f4xx.h.
| #define FSMC_SR2_IFS ((uint8_t)0x04) |
Interrupt Falling Edge status
Definition at line 3920 of file stm32f4xx.h.
| #define FSMC_SR2_ILEN ((uint8_t)0x10) |
Interrupt Level detection Enable bit
Definition at line 3922 of file stm32f4xx.h.
| #define FSMC_SR2_ILS ((uint8_t)0x02) |
Interrupt Level status
Definition at line 3919 of file stm32f4xx.h.
| #define FSMC_SR2_IREN ((uint8_t)0x08) |
Interrupt Rising Edge detection Enable bit
Definition at line 3921 of file stm32f4xx.h.
| #define FSMC_SR2_IRS ((uint8_t)0x01) |
Interrupt Rising Edge status
Definition at line 3918 of file stm32f4xx.h.
| #define FSMC_SR3_FEMPT ((uint8_t)0x40) |
FIFO empty
Definition at line 3933 of file stm32f4xx.h.
| #define FSMC_SR3_IFEN ((uint8_t)0x20) |
Interrupt Falling Edge detection Enable bit
Definition at line 3932 of file stm32f4xx.h.
| #define FSMC_SR3_IFS ((uint8_t)0x04) |
Interrupt Falling Edge status
Definition at line 3929 of file stm32f4xx.h.
| #define FSMC_SR3_ILEN ((uint8_t)0x10) |
Interrupt Level detection Enable bit
Definition at line 3931 of file stm32f4xx.h.
| #define FSMC_SR3_ILS ((uint8_t)0x02) |
Interrupt Level status
Definition at line 3928 of file stm32f4xx.h.
| #define FSMC_SR3_IREN ((uint8_t)0x08) |
Interrupt Rising Edge detection Enable bit
Definition at line 3930 of file stm32f4xx.h.
| #define FSMC_SR3_IRS ((uint8_t)0x01) |
Interrupt Rising Edge status
Definition at line 3927 of file stm32f4xx.h.
| #define FSMC_SR4_FEMPT ((uint8_t)0x40) |
FIFO empty
Definition at line 3942 of file stm32f4xx.h.
| #define FSMC_SR4_IFEN ((uint8_t)0x20) |
Interrupt Falling Edge detection Enable bit
Definition at line 3941 of file stm32f4xx.h.
| #define FSMC_SR4_IFS ((uint8_t)0x04) |
Interrupt Falling Edge status
Definition at line 3938 of file stm32f4xx.h.
| #define FSMC_SR4_ILEN ((uint8_t)0x10) |
Interrupt Level detection Enable bit
Definition at line 3940 of file stm32f4xx.h.
| #define FSMC_SR4_ILS ((uint8_t)0x02) |
Interrupt Level status
Definition at line 3937 of file stm32f4xx.h.
| #define FSMC_SR4_IREN ((uint8_t)0x08) |
Interrupt Rising Edge detection Enable bit
Definition at line 3939 of file stm32f4xx.h.
| #define FSMC_SR4_IRS ((uint8_t)0x01) |
Interrupt Rising Edge status
Definition at line 3936 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
Definition at line 4542 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
Definition at line 4543 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
Definition at line 4552 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
Definition at line 4553 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
Definition at line 4554 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
Definition at line 4555 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
Definition at line 4556 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
Definition at line 4557 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
Definition at line 4544 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
Definition at line 4545 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
Definition at line 4546 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
Definition at line 4547 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
Definition at line 4548 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
Definition at line 4549 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
Definition at line 4550 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
Definition at line 4551 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
Definition at line 4526 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
Definition at line 4527 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
Definition at line 4536 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
Definition at line 4537 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
Definition at line 4538 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
Definition at line 4539 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
Definition at line 4540 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
Definition at line 4541 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
Definition at line 4528 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
Definition at line 4529 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
Definition at line 4530 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
Definition at line 4531 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
Definition at line 4532 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
Definition at line 4533 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
Definition at line 4534 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
Definition at line 4535 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
Definition at line 4456 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
Definition at line 4457 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
Definition at line 4466 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
Definition at line 4467 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
Definition at line 4468 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
Definition at line 4469 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
Definition at line 4470 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
Definition at line 4471 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
Definition at line 4458 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
Definition at line 4459 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
Definition at line 4460 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
Definition at line 4461 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
Definition at line 4462 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
Definition at line 4463 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
Definition at line 4464 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
Definition at line 4465 of file stm32f4xx.h.
| #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
Definition at line 4243 of file stm32f4xx.h.
| #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
Definition at line 4244 of file stm32f4xx.h.
| #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
Definition at line 4245 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
Definition at line 4247 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
Definition at line 4283 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
Definition at line 4284 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
Definition at line 4285 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
Definition at line 4287 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
Definition at line 4288 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
Definition at line 4289 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
Definition at line 4291 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
Definition at line 4292 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
Definition at line 4293 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
Definition at line 4295 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
Definition at line 4296 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
Definition at line 4297 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
Definition at line 4299 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
Definition at line 4300 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
Definition at line 4301 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
Definition at line 4303 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
Definition at line 4304 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
Definition at line 4305 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
Definition at line 4248 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
Definition at line 4249 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
Definition at line 4251 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
Definition at line 4252 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
Definition at line 4253 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
Definition at line 4255 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
Definition at line 4256 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
Definition at line 4257 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
Definition at line 4259 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
Definition at line 4260 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
Definition at line 4261 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
Definition at line 4263 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
Definition at line 4264 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
Definition at line 4265 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
Definition at line 4267 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
Definition at line 4268 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
Definition at line 4269 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
Definition at line 4271 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
Definition at line 4272 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
Definition at line 4273 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
Definition at line 4275 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
Definition at line 4276 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
Definition at line 4277 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
Definition at line 4279 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
Definition at line 4280 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
Definition at line 4281 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
Definition at line 4491 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
Definition at line 4492 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
Definition at line 4501 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
Definition at line 4502 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
Definition at line 4503 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
Definition at line 4504 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
Definition at line 4505 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
Definition at line 4506 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
Definition at line 4493 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
Definition at line 4494 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
Definition at line 4495 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
Definition at line 4496 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
Definition at line 4497 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
Definition at line 4498 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
Definition at line 4499 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
Definition at line 4500 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
Definition at line 4326 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
Definition at line 4327 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
Definition at line 4328 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
Definition at line 4330 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
Definition at line 4366 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
Definition at line 4367 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
Definition at line 4368 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
Definition at line 4370 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
Definition at line 4371 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
Definition at line 4372 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
Definition at line 4374 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
Definition at line 4375 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
Definition at line 4376 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
Definition at line 4378 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
Definition at line 4379 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
Definition at line 4380 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
Definition at line 4382 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
Definition at line 4383 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
Definition at line 4384 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
Definition at line 4386 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
Definition at line 4387 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
Definition at line 4388 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
Definition at line 4331 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
Definition at line 4332 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
Definition at line 4334 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
Definition at line 4335 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
Definition at line 4336 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
Definition at line 4338 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
Definition at line 4339 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
Definition at line 4340 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
Definition at line 4342 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
Definition at line 4343 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
Definition at line 4344 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
Definition at line 4346 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
Definition at line 4347 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
Definition at line 4348 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
Definition at line 4350 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
Definition at line 4351 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
Definition at line 4352 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
Definition at line 4354 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
Definition at line 4355 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
Definition at line 4356 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
Definition at line 4358 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
Definition at line 4359 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
Definition at line 4360 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
Definition at line 4362 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
Definition at line 4363 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
Definition at line 4364 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
Definition at line 4473 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
Definition at line 4474 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
Definition at line 4483 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
Definition at line 4484 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
Definition at line 4485 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
Definition at line 4486 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
Definition at line 4487 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
Definition at line 4488 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
Definition at line 4475 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
Definition at line 4476 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
Definition at line 4477 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
Definition at line 4478 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
Definition at line 4479 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
Definition at line 4480 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
Definition at line 4481 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
Definition at line 4482 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
Definition at line 4508 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
Definition at line 4509 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
Definition at line 4518 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
Definition at line 4519 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
Definition at line 4520 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
Definition at line 4521 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
Definition at line 4522 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
Definition at line 4523 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
Definition at line 4510 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
Definition at line 4511 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
Definition at line 4512 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
Definition at line 4513 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
Definition at line 4514 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
Definition at line 4515 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
Definition at line 4516 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
Definition at line 4517 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
Definition at line 4308 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
Definition at line 4309 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
Definition at line 4318 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
Definition at line 4319 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
Definition at line 4320 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
Definition at line 4321 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
Definition at line 4322 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
Definition at line 4323 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
Definition at line 4310 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
Definition at line 4311 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
Definition at line 4312 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
Definition at line 4313 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
Definition at line 4314 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
Definition at line 4315 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
Definition at line 4316 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
Definition at line 4317 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
Definition at line 4391 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
Definition at line 4392 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
Definition at line 4393 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
Definition at line 4395 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
Definition at line 4431 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
Definition at line 4432 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
Definition at line 4433 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
Definition at line 4435 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
Definition at line 4436 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
Definition at line 4437 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
Definition at line 4439 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
Definition at line 4440 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
Definition at line 4441 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
Definition at line 4443 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
Definition at line 4444 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
Definition at line 4445 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
Definition at line 4447 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
Definition at line 4448 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
Definition at line 4449 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
Definition at line 4451 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
Definition at line 4452 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
Definition at line 4453 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
Definition at line 4396 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
Definition at line 4397 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
Definition at line 4399 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
Definition at line 4400 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
Definition at line 4401 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
Definition at line 4403 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
Definition at line 4404 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
Definition at line 4405 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
Definition at line 4407 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
Definition at line 4408 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
Definition at line 4409 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
Definition at line 4411 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
Definition at line 4412 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
Definition at line 4413 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
Definition at line 4415 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
Definition at line 4416 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
Definition at line 4417 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
Definition at line 4419 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
Definition at line 4420 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
Definition at line 4421 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
Definition at line 4423 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
Definition at line 4424 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
Definition at line 4425 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
Definition at line 4427 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
Definition at line 4428 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
Definition at line 4429 of file stm32f4xx.h.
| #define HASH_CR_ALGO ((uint32_t)0x00000080) |
Definition at line 4571 of file stm32f4xx.h.
| #define HASH_CR_DATATYPE ((uint32_t)0x00000030) |
Definition at line 4567 of file stm32f4xx.h.
| #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
Definition at line 4568 of file stm32f4xx.h.
| #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
Definition at line 4569 of file stm32f4xx.h.
| #define HASH_CR_DINNE ((uint32_t)0x00001000) |
Definition at line 4577 of file stm32f4xx.h.
| #define HASH_CR_DMAE ((uint32_t)0x00000008) |
Definition at line 4566 of file stm32f4xx.h.
| #define HASH_CR_INIT ((uint32_t)0x00000004) |
Definition at line 4565 of file stm32f4xx.h.
| #define HASH_CR_LKEY ((uint32_t)0x00010000) |
Definition at line 4578 of file stm32f4xx.h.
| #define HASH_CR_MODE ((uint32_t)0x00000040) |
Definition at line 4570 of file stm32f4xx.h.
| #define HASH_CR_NBW ((uint32_t)0x00000F00) |
Definition at line 4572 of file stm32f4xx.h.
| #define HASH_CR_NBW_0 ((uint32_t)0x00000100) |
Definition at line 4573 of file stm32f4xx.h.
| #define HASH_CR_NBW_1 ((uint32_t)0x00000200) |
Definition at line 4574 of file stm32f4xx.h.
| #define HASH_CR_NBW_2 ((uint32_t)0x00000400) |
Definition at line 4575 of file stm32f4xx.h.
| #define HASH_CR_NBW_3 ((uint32_t)0x00000800) |
Definition at line 4576 of file stm32f4xx.h.
| #define HASH_IMR_DCIM ((uint32_t)0x00000002) |
Definition at line 4591 of file stm32f4xx.h.
| #define HASH_IMR_DINIM ((uint32_t)0x00000001) |
Definition at line 4590 of file stm32f4xx.h.
| #define HASH_SR_BUSY ((uint32_t)0x00000008) |
Definition at line 4597 of file stm32f4xx.h.
| #define HASH_SR_DCIS ((uint32_t)0x00000002) |
Definition at line 4595 of file stm32f4xx.h.
| #define HASH_SR_DINIS ((uint32_t)0x00000001) |
Definition at line 4594 of file stm32f4xx.h.
| #define HASH_SR_DMAS ((uint32_t)0x00000004) |
Definition at line 4596 of file stm32f4xx.h.
| #define HASH_STR_DCAL ((uint32_t)0x00000100) |
Definition at line 4587 of file stm32f4xx.h.
| #define HASH_STR_NBW ((uint32_t)0x0000001F) |
Definition at line 4581 of file stm32f4xx.h.
| #define HASH_STR_NBW_0 ((uint32_t)0x00000001) |
Definition at line 4582 of file stm32f4xx.h.
| #define HASH_STR_NBW_1 ((uint32_t)0x00000002) |
Definition at line 4583 of file stm32f4xx.h.
| #define HASH_STR_NBW_2 ((uint32_t)0x00000004) |
Definition at line 4584 of file stm32f4xx.h.
| #define HASH_STR_NBW_3 ((uint32_t)0x00000008) |
Definition at line 4585 of file stm32f4xx.h.
| #define HASH_STR_NBW_4 ((uint32_t)0x00000010) |
Definition at line 4586 of file stm32f4xx.h.
| #define I2C_CCR_CCR ((uint16_t)0x0FFF) |
Clock Control Register in Fast/Standard mode (Master mode)
Definition at line 4686 of file stm32f4xx.h.
| #define I2C_CCR_DUTY ((uint16_t)0x4000) |
Fast Mode Duty Cycle
Definition at line 4687 of file stm32f4xx.h.
| #define I2C_CCR_FS ((uint16_t)0x8000) |
I2C Master Mode Selection
Definition at line 4688 of file stm32f4xx.h.
| #define I2C_CR1_ACK ((uint16_t)0x0400) |
Acknowledge Enable
Definition at line 4614 of file stm32f4xx.h.
| #define I2C_CR1_ALERT ((uint16_t)0x2000) |
SMBus Alert
Definition at line 4617 of file stm32f4xx.h.
| #define I2C_CR1_ENARP ((uint16_t)0x0010) |
ARP Enable
Definition at line 4608 of file stm32f4xx.h.
| #define I2C_CR1_ENGC ((uint16_t)0x0040) |
General Call Enable
Definition at line 4610 of file stm32f4xx.h.
| #define I2C_CR1_ENPEC ((uint16_t)0x0020) |
PEC Enable
Definition at line 4609 of file stm32f4xx.h.
| #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
Clock Stretching Disable (Slave mode)
Definition at line 4611 of file stm32f4xx.h.
| #define I2C_CR1_PE ((uint16_t)0x0001) |
Peripheral Enable
Definition at line 4605 of file stm32f4xx.h.
| #define I2C_CR1_PEC ((uint16_t)0x1000) |
Packet Error Checking
Definition at line 4616 of file stm32f4xx.h.
| #define I2C_CR1_POS ((uint16_t)0x0800) |
Acknowledge/PEC Position (for data reception)
Definition at line 4615 of file stm32f4xx.h.
| #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
SMBus Type
Definition at line 4607 of file stm32f4xx.h.
| #define I2C_CR1_SMBUS ((uint16_t)0x0002) |
SMBus Mode
Definition at line 4606 of file stm32f4xx.h.
| #define I2C_CR1_START ((uint16_t)0x0100) |
Start Generation
Definition at line 4612 of file stm32f4xx.h.
| #define I2C_CR1_STOP ((uint16_t)0x0200) |
Stop Generation
Definition at line 4613 of file stm32f4xx.h.
| #define I2C_CR1_SWRST ((uint16_t)0x8000) |
Software Reset
Definition at line 4618 of file stm32f4xx.h.
| #define I2C_CR2_DMAEN ((uint16_t)0x0800) |
DMA Requests Enable
Definition at line 4632 of file stm32f4xx.h.
| #define I2C_CR2_FREQ ((uint16_t)0x003F) |
FREQ[5:0] bits (Peripheral Clock Frequency)
Definition at line 4621 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 4622 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 4623 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 4624 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 4625 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 4626 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 4627 of file stm32f4xx.h.
| #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
Buffer Interrupt Enable
Definition at line 4631 of file stm32f4xx.h.
| #define I2C_CR2_ITERREN ((uint16_t)0x0100) |
Error Interrupt Enable
Definition at line 4629 of file stm32f4xx.h.
| #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
Event Interrupt Enable
Definition at line 4630 of file stm32f4xx.h.
| #define I2C_CR2_LAST ((uint16_t)0x1000) |
DMA Last Transfer
Definition at line 4633 of file stm32f4xx.h.
| #define I2C_DR_DR ((uint8_t)0xFF) |
8-bit Data Register
Definition at line 4657 of file stm32f4xx.h.
| #define I2C_OAR1_ADD0 ((uint16_t)0x0001) |
Bit 0
Definition at line 4639 of file stm32f4xx.h.
| #define I2C_OAR1_ADD1 ((uint16_t)0x0002) |
Bit 1
Definition at line 4640 of file stm32f4xx.h.
| #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
Interface Address
Definition at line 4636 of file stm32f4xx.h.
| #define I2C_OAR1_ADD2 ((uint16_t)0x0004) |
Bit 2
Definition at line 4641 of file stm32f4xx.h.
| #define I2C_OAR1_ADD3 ((uint16_t)0x0008) |
Bit 3
Definition at line 4642 of file stm32f4xx.h.
| #define I2C_OAR1_ADD4 ((uint16_t)0x0010) |
Bit 4
Definition at line 4643 of file stm32f4xx.h.
| #define I2C_OAR1_ADD5 ((uint16_t)0x0020) |
Bit 5
Definition at line 4644 of file stm32f4xx.h.
| #define I2C_OAR1_ADD6 ((uint16_t)0x0040) |
Bit 6
Definition at line 4645 of file stm32f4xx.h.
| #define I2C_OAR1_ADD7 ((uint16_t)0x0080) |
Bit 7
Definition at line 4646 of file stm32f4xx.h.
| #define I2C_OAR1_ADD8 ((uint16_t)0x0100) |
Bit 8
Definition at line 4647 of file stm32f4xx.h.
| #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
Interface Address
Definition at line 4637 of file stm32f4xx.h.
| #define I2C_OAR1_ADD9 ((uint16_t)0x0200) |
Bit 9
Definition at line 4648 of file stm32f4xx.h.
| #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
Addressing Mode (Slave mode)
Definition at line 4650 of file stm32f4xx.h.
| #define I2C_OAR2_ADD2 ((uint8_t)0xFE) |
Interface address
Definition at line 4654 of file stm32f4xx.h.
| #define I2C_OAR2_ENDUAL ((uint8_t)0x01) |
Dual addressing mode enable
Definition at line 4653 of file stm32f4xx.h.
| #define I2C_SR1_ADD10 ((uint16_t)0x0008) |
10-bit header sent (Master mode)
Definition at line 4663 of file stm32f4xx.h.
| #define I2C_SR1_ADDR ((uint16_t)0x0002) |
Address sent (master mode)/matched (slave mode)
Definition at line 4661 of file stm32f4xx.h.
| #define I2C_SR1_AF ((uint16_t)0x0400) |
Acknowledge Failure
Definition at line 4669 of file stm32f4xx.h.
| #define I2C_SR1_ARLO ((uint16_t)0x0200) |
Arbitration Lost (master mode)
Definition at line 4668 of file stm32f4xx.h.
| #define I2C_SR1_BERR ((uint16_t)0x0100) |
Bus Error
Definition at line 4667 of file stm32f4xx.h.
| #define I2C_SR1_BTF ((uint16_t)0x0004) |
Byte Transfer Finished
Definition at line 4662 of file stm32f4xx.h.
| #define I2C_SR1_OVR ((uint16_t)0x0800) |
Overrun/Underrun
Definition at line 4670 of file stm32f4xx.h.
| #define I2C_SR1_PECERR ((uint16_t)0x1000) |
PEC Error in reception
Definition at line 4671 of file stm32f4xx.h.
| #define I2C_SR1_RXNE ((uint16_t)0x0040) |
Data Register not Empty (receivers)
Definition at line 4665 of file stm32f4xx.h.
| #define I2C_SR1_SB ((uint16_t)0x0001) |
Start Bit (Master mode)
Definition at line 4660 of file stm32f4xx.h.
| #define I2C_SR1_SMBALERT ((uint16_t)0x8000) |
SMBus Alert
Definition at line 4673 of file stm32f4xx.h.
| #define I2C_SR1_STOPF ((uint16_t)0x0010) |
Stop detection (Slave mode)
Definition at line 4664 of file stm32f4xx.h.
| #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
Timeout or Tlow Error
Definition at line 4672 of file stm32f4xx.h.
| #define I2C_SR1_TXE ((uint16_t)0x0080) |
Data Register Empty (transmitters)
Definition at line 4666 of file stm32f4xx.h.
| #define I2C_SR2_BUSY ((uint16_t)0x0002) |
Bus Busy
Definition at line 4677 of file stm32f4xx.h.
| #define I2C_SR2_DUALF ((uint16_t)0x0080) |
Dual Flag (Slave mode)
Definition at line 4682 of file stm32f4xx.h.
| #define I2C_SR2_GENCALL ((uint16_t)0x0010) |
General Call Address (Slave mode)
Definition at line 4679 of file stm32f4xx.h.
| #define I2C_SR2_MSL ((uint16_t)0x0001) |
Master/Slave
Definition at line 4676 of file stm32f4xx.h.
| #define I2C_SR2_PEC ((uint16_t)0xFF00) |
Packet Error Checking Register
Definition at line 4683 of file stm32f4xx.h.
| #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
SMBus Device Default Address (Slave mode)
Definition at line 4680 of file stm32f4xx.h.
| #define I2C_SR2_SMBHOST ((uint16_t)0x0040) |
SMBus Host Header (Slave mode)
Definition at line 4681 of file stm32f4xx.h.
| #define I2C_SR2_TRA ((uint16_t)0x0004) |
Transmitter/Receiver
Definition at line 4678 of file stm32f4xx.h.
| #define I2C_TRISE_TRISE ((uint8_t)0x3F) |
Maximum Rise Time in Fast/Standard mode (Master mode)
Definition at line 4691 of file stm32f4xx.h.
| #define IWDG_KR_KEY ((uint16_t)0xFFFF) |
Key value (write only, read 0000h)
Definition at line 4699 of file stm32f4xx.h.
| #define IWDG_PR_PR ((uint8_t)0x07) |
PR[2:0] (Prescaler divider)
Definition at line 4702 of file stm32f4xx.h.
| #define IWDG_PR_PR_0 ((uint8_t)0x01) |
Bit 0
Definition at line 4703 of file stm32f4xx.h.
| #define IWDG_PR_PR_1 ((uint8_t)0x02) |
Bit 1
Definition at line 4704 of file stm32f4xx.h.
| #define IWDG_PR_PR_2 ((uint8_t)0x04) |
Bit 2
Definition at line 4705 of file stm32f4xx.h.
| #define IWDG_RLR_RL ((uint16_t)0x0FFF) |
Watchdog counter reload value
Definition at line 4708 of file stm32f4xx.h.
| #define IWDG_SR_PVU ((uint8_t)0x01) |
Watchdog prescaler value update
Definition at line 4711 of file stm32f4xx.h.
| #define IWDG_SR_RVU ((uint8_t)0x02) |
Watchdog counter reload value update
Definition at line 4712 of file stm32f4xx.h.
| #define PWR_CR_CSBF ((uint16_t)0x0008) |
Clear Standby Flag
Definition at line 4723 of file stm32f4xx.h.
| #define PWR_CR_CWUF ((uint16_t)0x0004) |
Clear Wakeup Flag
Definition at line 4722 of file stm32f4xx.h.
| #define PWR_CR_DBP ((uint16_t)0x0100) |
Disable Backup Domain write protection
Definition at line 4742 of file stm32f4xx.h.
| #define PWR_CR_FPDS ((uint16_t)0x0200) |
Flash power down in Stop mode
Definition at line 4743 of file stm32f4xx.h.
| #define PWR_CR_LPDS ((uint16_t)0x0001) |
Low-Power Deepsleep
Definition at line 4720 of file stm32f4xx.h.
| #define PWR_CR_PDDS ((uint16_t)0x0002) |
Power Down Deepsleep
Definition at line 4721 of file stm32f4xx.h.
| #define PWR_CR_PLS ((uint16_t)0x00E0) |
PLS[2:0] bits (PVD Level Selection)
Definition at line 4726 of file stm32f4xx.h.
| #define PWR_CR_PLS_0 ((uint16_t)0x0020) |
Bit 0
Definition at line 4727 of file stm32f4xx.h.
| #define PWR_CR_PLS_1 ((uint16_t)0x0040) |
Bit 1
Definition at line 4728 of file stm32f4xx.h.
| #define PWR_CR_PLS_2 ((uint16_t)0x0080) |
Bit 2 PVD level configuration
Definition at line 4729 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
PVD level 0
Definition at line 4733 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
PVD level 1
Definition at line 4734 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
PVD level 2
Definition at line 4735 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
PVD level 3
Definition at line 4736 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
PVD level 4
Definition at line 4737 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
PVD level 5
Definition at line 4738 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
PVD level 6
Definition at line 4739 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
PVD level 7
Definition at line 4740 of file stm32f4xx.h.
| #define PWR_CR_PMODE PWR_CR_VOS |
Definition at line 4746 of file stm32f4xx.h.
| #define PWR_CR_PVDE ((uint16_t)0x0010) |
Power Voltage Detector Enable
Definition at line 4724 of file stm32f4xx.h.
| #define PWR_CR_VOS ((uint16_t)0x4000) |
Regulator voltage scaling output selection
Definition at line 4744 of file stm32f4xx.h.
| #define PWR_CSR_BRE ((uint16_t)0x0200) |
Backup regulator enable
Definition at line 4754 of file stm32f4xx.h.
| #define PWR_CSR_BRR ((uint16_t)0x0008) |
Backup regulator ready
Definition at line 4752 of file stm32f4xx.h.
| #define PWR_CSR_EWUP ((uint16_t)0x0100) |
Enable WKUP pin
Definition at line 4753 of file stm32f4xx.h.
| #define PWR_CSR_PVDO ((uint16_t)0x0004) |
PVD Output
Definition at line 4751 of file stm32f4xx.h.
| #define PWR_CSR_REGRDY PWR_CSR_VOSRDY |
Definition at line 4757 of file stm32f4xx.h.
| #define PWR_CSR_SBF ((uint16_t)0x0002) |
Standby Flag
Definition at line 4750 of file stm32f4xx.h.
| #define PWR_CSR_VOSRDY ((uint16_t)0x4000) |
Regulator voltage scaling output selection ready
Definition at line 4755 of file stm32f4xx.h.
| #define PWR_CSR_WUF ((uint16_t)0x0001) |
Wakeup Flag
Definition at line 4749 of file stm32f4xx.h.
| #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
Definition at line 5016 of file stm32f4xx.h.
| #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
Definition at line 5017 of file stm32f4xx.h.
| #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
Definition at line 5015 of file stm32f4xx.h.
| #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
Definition at line 5018 of file stm32f4xx.h.
| #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
Definition at line 5019 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
Definition at line 5020 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
Definition at line 5023 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
Definition at line 5022 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
Definition at line 5021 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
Definition at line 5006 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
Definition at line 5007 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
Definition at line 5008 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
Definition at line 5009 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
Definition at line 5010 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
Definition at line 5011 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
Definition at line 5012 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
Definition at line 5013 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
Definition at line 5014 of file stm32f4xx.h.
| #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
Definition at line 5024 of file stm32f4xx.h.
| #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
Definition at line 5025 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
Definition at line 5091 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
Definition at line 5087 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
Definition at line 5092 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
Definition at line 5093 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
Definition at line 5094 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
Definition at line 5097 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
Definition at line 5096 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
Definition at line 5095 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
Definition at line 5088 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
Definition at line 5078 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
Definition at line 5079 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
Definition at line 5080 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
Definition at line 5081 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
Definition at line 5082 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
Definition at line 5083 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
Definition at line 5084 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
Definition at line 5085 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
Definition at line 5086 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
Definition at line 5098 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
Definition at line 5099 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
Definition at line 5089 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
Definition at line 5090 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
Definition at line 4949 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
Definition at line 4950 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
Definition at line 4951 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
Definition at line 4952 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
Definition at line 4940 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
Definition at line 4941 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
Definition at line 4942 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
Definition at line 4943 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
Definition at line 4944 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
Definition at line 4945 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
Definition at line 4946 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
Definition at line 4947 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
Definition at line 4948 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) |
Definition at line 4953 of file stm32f4xx.h.
| #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
Definition at line 5029 of file stm32f4xx.h.
| #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
Definition at line 5028 of file stm32f4xx.h.
| #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
Definition at line 5030 of file stm32f4xx.h.
| #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
Definition at line 5032 of file stm32f4xx.h.
| #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
Definition at line 5031 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
Definition at line 5103 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
Definition at line 5102 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
Definition at line 5104 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
Definition at line 5106 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
Definition at line 5105 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
Definition at line 4957 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
Definition at line 4956 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020) |
Definition at line 4958 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
Definition at line 4960 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
Definition at line 4959 of file stm32f4xx.h.
| #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) |
Definition at line 5035 of file stm32f4xx.h.
| #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) |
Definition at line 5109 of file stm32f4xx.h.
| #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) |
Definition at line 4963 of file stm32f4xx.h.
| #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
Definition at line 5057 of file stm32f4xx.h.
| #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
Definition at line 5058 of file stm32f4xx.h.
| #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
Definition at line 5060 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
Definition at line 5054 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
Definition at line 5055 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
Definition at line 5056 of file stm32f4xx.h.
| #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
Definition at line 5059 of file stm32f4xx.h.
| #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
Definition at line 5048 of file stm32f4xx.h.
| #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
Definition at line 5049 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
Definition at line 5044 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
Definition at line 5045 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
Definition at line 5046 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
Definition at line 5038 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
Definition at line 5039 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
Definition at line 5040 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
Definition at line 5041 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
Definition at line 5042 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
Definition at line 5043 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
Definition at line 5052 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
Definition at line 5053 of file stm32f4xx.h.
| #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
Definition at line 5050 of file stm32f4xx.h.
| #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
Definition at line 5051 of file stm32f4xx.h.
| #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
Definition at line 5047 of file stm32f4xx.h.
| #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
Definition at line 5131 of file stm32f4xx.h.
| #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
Definition at line 5132 of file stm32f4xx.h.
| #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
Definition at line 5134 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
Definition at line 5128 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
Definition at line 5129 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
Definition at line 5130 of file stm32f4xx.h.
| #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
Definition at line 5133 of file stm32f4xx.h.
| #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
Definition at line 5122 of file stm32f4xx.h.
| #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
Definition at line 5123 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
Definition at line 5118 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
Definition at line 5119 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
Definition at line 5120 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
Definition at line 5112 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
Definition at line 5113 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
Definition at line 5114 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
Definition at line 5115 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
Definition at line 5116 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
Definition at line 5117 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
Definition at line 5126 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
Definition at line 5127 of file stm32f4xx.h.
| #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
Definition at line 5124 of file stm32f4xx.h.
| #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
Definition at line 5125 of file stm32f4xx.h.
| #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
Definition at line 5121 of file stm32f4xx.h.
| #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
Definition at line 4985 of file stm32f4xx.h.
| #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
Definition at line 4986 of file stm32f4xx.h.
| #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
Definition at line 4988 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
Definition at line 4982 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
Definition at line 4983 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
Definition at line 4984 of file stm32f4xx.h.
| #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
Definition at line 4987 of file stm32f4xx.h.
| #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000) |
Definition at line 4976 of file stm32f4xx.h.
| #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000) |
Definition at line 4977 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
Definition at line 4972 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
Definition at line 4973 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
Definition at line 4974 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
Definition at line 4966 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
Definition at line 4967 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
Definition at line 4968 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
Definition at line 4969 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
Definition at line 4970 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
Definition at line 4971 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
Definition at line 4980 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
Definition at line 4981 of file stm32f4xx.h.
| #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
Definition at line 4978 of file stm32f4xx.h.
| #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
Definition at line 4979 of file stm32f4xx.h.
| #define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) |
Definition at line 4975 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
Definition at line 5067 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
Definition at line 5068 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
Definition at line 5069 of file stm32f4xx.h.
| #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
Definition at line 5070 of file stm32f4xx.h.
| #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
Definition at line 5071 of file stm32f4xx.h.
| #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
Definition at line 5072 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
Definition at line 5074 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
Definition at line 5073 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
Definition at line 5063 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
Definition at line 5064 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
Definition at line 5075 of file stm32f4xx.h.
| #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
Definition at line 5065 of file stm32f4xx.h.
| #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
Definition at line 5066 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
Definition at line 5141 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
Definition at line 5142 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
Definition at line 5143 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
Definition at line 5144 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
Definition at line 5145 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
Definition at line 5146 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
Definition at line 5148 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
Definition at line 5149 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
Definition at line 5137 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
Definition at line 5138 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
Definition at line 5147 of file stm32f4xx.h.
| #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
Definition at line 5139 of file stm32f4xx.h.
| #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
Definition at line 5140 of file stm32f4xx.h.
| #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
Definition at line 4995 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
Definition at line 4996 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
Definition at line 5003 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
Definition at line 4997 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
Definition at line 4998 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
Definition at line 5000 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
Definition at line 5001 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
Definition at line 4991 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
Definition at line 4992 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
Definition at line 4999 of file stm32f4xx.h.
| #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
Definition at line 4993 of file stm32f4xx.h.
| #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
Definition at line 4994 of file stm32f4xx.h.
| #define RCC_BDCR_BDRST ((uint32_t)0x00010000) |
Definition at line 5161 of file stm32f4xx.h.
| #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
Definition at line 5154 of file stm32f4xx.h.
| #define RCC_BDCR_LSEON ((uint32_t)0x00000001) |
Definition at line 5152 of file stm32f4xx.h.
| #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
Definition at line 5153 of file stm32f4xx.h.
| #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
Definition at line 5160 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
Definition at line 5156 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
Definition at line 5157 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
Definition at line 5158 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
HPRE[3:0] bits (AHB prescaler)
Definition at line 4848 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 4849 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 4850 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 4851 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 4852 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
SYSCLK not divided
Definition at line 4854 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
SYSCLK divided by 128
Definition at line 4860 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
SYSCLK divided by 16
Definition at line 4858 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
SYSCLK divided by 2
Definition at line 4855 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
SYSCLK divided by 256
Definition at line 4861 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
SYSCLK divided by 4
Definition at line 4856 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
SYSCLK divided by 512 PPRE1 configuration
Definition at line 4862 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
SYSCLK divided by 64
Definition at line 4859 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
SYSCLK divided by 8
Definition at line 4857 of file stm32f4xx.h.
| #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
Definition at line 4901 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
Definition at line 4897 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
Definition at line 4898 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
Definition at line 4899 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
Definition at line 4903 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
Definition at line 4904 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
Definition at line 4905 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
Definition at line 4906 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
Definition at line 4913 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
Definition at line 4914 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
Definition at line 4915 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
Definition at line 4908 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
Definition at line 4909 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
Definition at line 4910 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
Definition at line 4911 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
PRE1[2:0] bits (APB1 prescaler)
Definition at line 4865 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 4866 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 4867 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 4868 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
HCLK not divided
Definition at line 4870 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
HCLK divided by 16 PPRE2 configuration
Definition at line 4874 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
HCLK divided by 2
Definition at line 4871 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
HCLK divided by 4
Definition at line 4872 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
HCLK divided by 8
Definition at line 4873 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
PRE2[2:0] bits (APB2 prescaler)
Definition at line 4877 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 4878 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 4879 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 4880 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
HCLK not divided
Definition at line 4882 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) |
HCLK divided by 16 RTCPRE configuration
Definition at line 4886 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
HCLK divided by 2
Definition at line 4883 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
HCLK divided by 4
Definition at line 4884 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
HCLK divided by 8
Definition at line 4885 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
Definition at line 4889 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
Definition at line 4890 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
Definition at line 4891 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
Definition at line 4892 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
Definition at line 4893 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
MCO1 configuration
Definition at line 4894 of file stm32f4xx.h.
| #define RCC_CFGR_SW ((uint32_t)0x00000003) |
< SW configuration SW[1:0] bits (System clock Switch)
Definition at line 4830 of file stm32f4xx.h.
| #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 4831 of file stm32f4xx.h.
| #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 4832 of file stm32f4xx.h.
| #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
HSE selected as system clock
Definition at line 4835 of file stm32f4xx.h.
| #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
HSI selected as system clock
Definition at line 4834 of file stm32f4xx.h.
| #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
PLL selected as system clock SWS configuration
Definition at line 4836 of file stm32f4xx.h.
| #define RCC_CFGR_SWS ((uint32_t)0x0000000C) |
SWS[1:0] bits (System Clock Switch Status)
Definition at line 4839 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 4840 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 4841 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
HSE oscillator used as system clock
Definition at line 4844 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
HSI oscillator used as system clock
Definition at line 4843 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
PLL used as system clock HPRE configuration
Definition at line 4845 of file stm32f4xx.h.
| #define RCC_CIR_CSSC ((uint32_t)0x00800000) |
Definition at line 4937 of file stm32f4xx.h.
| #define RCC_CIR_CSSF ((uint32_t)0x00000080) |
Definition at line 4924 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
Definition at line 4934 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
Definition at line 4921 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
Definition at line 4928 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
Definition at line 4933 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
Definition at line 4920 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
Definition at line 4927 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
Definition at line 4932 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
Definition at line 4919 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
Definition at line 4926 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
Definition at line 4931 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
Definition at line 4918 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
Definition at line 4925 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
Definition at line 4936 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
Definition at line 4923 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
Definition at line 4930 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
Definition at line 4935 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
Definition at line 4922 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
Definition at line 4929 of file stm32f4xx.h.
| #define RCC_CR_CSSON ((uint32_t)0x00080000) |
Definition at line 4788 of file stm32f4xx.h.
| #define RCC_CR_HSEBYP ((uint32_t)0x00040000) |
Definition at line 4787 of file stm32f4xx.h.
| #define RCC_CR_HSEON ((uint32_t)0x00010000) |
Definition at line 4785 of file stm32f4xx.h.
| #define RCC_CR_HSERDY ((uint32_t)0x00020000) |
Definition at line 4786 of file stm32f4xx.h.
| #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
Definition at line 4775 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100 |
Bit 0
Definition at line 4776 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200 |
Bit 1
Definition at line 4777 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400 |
Bit 2
Definition at line 4778 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800 |
Bit 3
Definition at line 4779 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000 |
Bit 4
Definition at line 4780 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000 |
Bit 5
Definition at line 4781 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000 |
Bit 6
Definition at line 4782 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000 |
Bit 7
Definition at line 4783 of file stm32f4xx.h.
| #define RCC_CR_HSION ((uint32_t)0x00000001) |
Definition at line 4765 of file stm32f4xx.h.
| #define RCC_CR_HSIRDY ((uint32_t)0x00000002) |
Definition at line 4766 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
Definition at line 4768 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008 |
Bit 0
Definition at line 4769 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010 |
Bit 1
Definition at line 4770 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020 |
Bit 2
Definition at line 4771 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040 |
Bit 3
Definition at line 4772 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080 |
Bit 4
Definition at line 4773 of file stm32f4xx.h.
| #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
Definition at line 4791 of file stm32f4xx.h.
| #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
Definition at line 4792 of file stm32f4xx.h.
| #define RCC_CR_PLLON ((uint32_t)0x01000000) |
Definition at line 4789 of file stm32f4xx.h.
| #define RCC_CR_PLLRDY ((uint32_t)0x02000000) |
Definition at line 4790 of file stm32f4xx.h.
| #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
Definition at line 5167 of file stm32f4xx.h.
| #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
Definition at line 5173 of file stm32f4xx.h.
| #define RCC_CSR_LSION ((uint32_t)0x00000001) |
Definition at line 5164 of file stm32f4xx.h.
| #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
Definition at line 5165 of file stm32f4xx.h.
| #define RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
Definition at line 5168 of file stm32f4xx.h.
| #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
Definition at line 5169 of file stm32f4xx.h.
| #define RCC_CSR_RMVF ((uint32_t)0x01000000) |
Definition at line 5166 of file stm32f4xx.h.
| #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
Definition at line 5170 of file stm32f4xx.h.
| #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
Definition at line 5171 of file stm32f4xx.h.
| #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
Definition at line 5172 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
Definition at line 4795 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
Definition at line 4796 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
Definition at line 4797 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
Definition at line 4798 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
Definition at line 4799 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
Definition at line 4800 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
Definition at line 4801 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
Definition at line 4803 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
Definition at line 4804 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
Definition at line 4805 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
Definition at line 4806 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
Definition at line 4807 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
Definition at line 4808 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
Definition at line 4809 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
Definition at line 4810 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
Definition at line 4811 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
Definition at line 4812 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
Definition at line 4814 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
Definition at line 4815 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
Definition at line 4816 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
Definition at line 4822 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
Definition at line 4823 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
Definition at line 4824 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
Definition at line 4825 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
Definition at line 4826 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
Definition at line 4818 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
Definition at line 4819 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
Definition at line 4820 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
Definition at line 5182 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
Definition at line 5183 of file stm32f4xx.h.
| #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
Definition at line 5177 of file stm32f4xx.h.
| #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
Definition at line 5176 of file stm32f4xx.h.
| #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
Definition at line 5178 of file stm32f4xx.h.
| #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
Definition at line 5179 of file stm32f4xx.h.
| #define RNG_CR_IE ((uint32_t)0x00000008) |
Definition at line 5192 of file stm32f4xx.h.
| #define RNG_CR_RNGEN ((uint32_t)0x00000004) |
Definition at line 5191 of file stm32f4xx.h.
| #define RNG_SR_CECS ((uint32_t)0x00000002) |
Definition at line 5196 of file stm32f4xx.h.
| #define RNG_SR_CEIS ((uint32_t)0x00000020) |
Definition at line 5198 of file stm32f4xx.h.
| #define RNG_SR_DRDY ((uint32_t)0x00000001) |
Definition at line 5195 of file stm32f4xx.h.
| #define RNG_SR_SECS ((uint32_t)0x00000004) |
Definition at line 5197 of file stm32f4xx.h.
| #define RNG_SR_SEIS ((uint32_t)0x00000040) |
Definition at line 5199 of file stm32f4xx.h.
| #define RTC_ALRMAR_DT ((uint32_t)0x30000000) |
Definition at line 5324 of file stm32f4xx.h.
| #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
Definition at line 5325 of file stm32f4xx.h.
| #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
Definition at line 5326 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
Definition at line 5327 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
Definition at line 5328 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
Definition at line 5329 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
Definition at line 5330 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
Definition at line 5331 of file stm32f4xx.h.
| #define RTC_ALRMAR_HT ((uint32_t)0x00300000) |
Definition at line 5334 of file stm32f4xx.h.
| #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
Definition at line 5335 of file stm32f4xx.h.
| #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
Definition at line 5336 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
Definition at line 5337 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
Definition at line 5338 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
Definition at line 5339 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
Definition at line 5340 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
Definition at line 5341 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
Definition at line 5343 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 5344 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 5345 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 5346 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
Definition at line 5347 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 5348 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 5349 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 5350 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 5351 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
Definition at line 5352 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
Definition at line 5342 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
Definition at line 5332 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
Definition at line 5322 of file stm32f4xx.h.
| #define RTC_ALRMAR_PM ((uint32_t)0x00400000) |
Definition at line 5333 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST ((uint32_t)0x00000070) |
Definition at line 5353 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
Definition at line 5354 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
Definition at line 5355 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
Definition at line 5356 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
Definition at line 5357 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
Definition at line 5358 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
Definition at line 5359 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
Definition at line 5360 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
Definition at line 5361 of file stm32f4xx.h.
| #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
Definition at line 5323 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
Definition at line 5503 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
Definition at line 5504 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
Definition at line 5505 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
Definition at line 5506 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
Definition at line 5507 of file stm32f4xx.h.
| #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
Definition at line 5508 of file stm32f4xx.h.
| #define RTC_ALRMBR_DT ((uint32_t)0x30000000) |
Definition at line 5366 of file stm32f4xx.h.
| #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
Definition at line 5367 of file stm32f4xx.h.
| #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
Definition at line 5368 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
Definition at line 5369 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
Definition at line 5370 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
Definition at line 5371 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
Definition at line 5372 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
Definition at line 5373 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT ((uint32_t)0x00300000) |
Definition at line 5376 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
Definition at line 5377 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
Definition at line 5378 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
Definition at line 5379 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
Definition at line 5380 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
Definition at line 5381 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
Definition at line 5382 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
Definition at line 5383 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
Definition at line 5385 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 5386 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 5387 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 5388 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
Definition at line 5389 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 5390 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 5391 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 5392 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 5393 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
Definition at line 5394 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
Definition at line 5384 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
Definition at line 5374 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
Definition at line 5364 of file stm32f4xx.h.
| #define RTC_ALRMBR_PM ((uint32_t)0x00400000) |
Definition at line 5375 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST ((uint32_t)0x00000070) |
Definition at line 5395 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
Definition at line 5396 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
Definition at line 5397 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
Definition at line 5398 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
Definition at line 5399 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
Definition at line 5400 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
Definition at line 5401 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
Definition at line 5402 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
Definition at line 5403 of file stm32f4xx.h.
| #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
Definition at line 5365 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
Definition at line 5511 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
Definition at line 5512 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
Definition at line 5513 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
Definition at line 5514 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
Definition at line 5515 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
Definition at line 5516 of file stm32f4xx.h.
| #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
Definition at line 5519 of file stm32f4xx.h.
| #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
Definition at line 5549 of file stm32f4xx.h.
| #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
Definition at line 5552 of file stm32f4xx.h.
| #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
Definition at line 5555 of file stm32f4xx.h.
| #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
Definition at line 5558 of file stm32f4xx.h.
| #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
Definition at line 5561 of file stm32f4xx.h.
| #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
Definition at line 5564 of file stm32f4xx.h.
| #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
Definition at line 5567 of file stm32f4xx.h.
| #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
Definition at line 5570 of file stm32f4xx.h.
| #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
Definition at line 5573 of file stm32f4xx.h.
| #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
Definition at line 5576 of file stm32f4xx.h.
| #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
Definition at line 5522 of file stm32f4xx.h.
| #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
Definition at line 5525 of file stm32f4xx.h.
| #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
Definition at line 5528 of file stm32f4xx.h.
| #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
Definition at line 5531 of file stm32f4xx.h.
| #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
Definition at line 5534 of file stm32f4xx.h.
| #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
Definition at line 5537 of file stm32f4xx.h.
| #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
Definition at line 5540 of file stm32f4xx.h.
| #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
Definition at line 5543 of file stm32f4xx.h.
| #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
Definition at line 5546 of file stm32f4xx.h.
| #define RTC_CALIBR_DC ((uint32_t)0x0000001F) |
Definition at line 5319 of file stm32f4xx.h.
| #define RTC_CALIBR_DCS ((uint32_t)0x00000080) |
Definition at line 5318 of file stm32f4xx.h.
| #define RTC_CALR_CALM ((uint32_t)0x000001FF) |
Definition at line 5471 of file stm32f4xx.h.
| #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
Definition at line 5472 of file stm32f4xx.h.
| #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
Definition at line 5473 of file stm32f4xx.h.
| #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
Definition at line 5474 of file stm32f4xx.h.
| #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
Definition at line 5475 of file stm32f4xx.h.
| #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
Definition at line 5476 of file stm32f4xx.h.
| #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
Definition at line 5477 of file stm32f4xx.h.
| #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
Definition at line 5478 of file stm32f4xx.h.
| #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
Definition at line 5479 of file stm32f4xx.h.
| #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
Definition at line 5480 of file stm32f4xx.h.
| #define RTC_CALR_CALP ((uint32_t)0x00008000) |
Definition at line 5468 of file stm32f4xx.h.
| #define RTC_CALR_CALW16 ((uint32_t)0x00002000) |
Definition at line 5470 of file stm32f4xx.h.
| #define RTC_CALR_CALW8 ((uint32_t)0x00004000) |
Definition at line 5469 of file stm32f4xx.h.
| #define RTC_CR_ADD1H ((uint32_t)0x00010000) |
Definition at line 5274 of file stm32f4xx.h.
| #define RTC_CR_ALRAE ((uint32_t)0x00000100) |
Definition at line 5282 of file stm32f4xx.h.
| #define RTC_CR_ALRAIE ((uint32_t)0x00001000) |
Definition at line 5278 of file stm32f4xx.h.
| #define RTC_CR_ALRBE ((uint32_t)0x00000200) |
Definition at line 5281 of file stm32f4xx.h.
| #define RTC_CR_ALRBIE ((uint32_t)0x00002000) |
Definition at line 5277 of file stm32f4xx.h.
| #define RTC_CR_BCK ((uint32_t)0x00040000) |
Definition at line 5272 of file stm32f4xx.h.
| #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
Definition at line 5285 of file stm32f4xx.h.
| #define RTC_CR_COE ((uint32_t)0x00800000) |
Definition at line 5266 of file stm32f4xx.h.
| #define RTC_CR_COSEL ((uint32_t)0x00080000) |
Definition at line 5271 of file stm32f4xx.h.
| #define RTC_CR_DCE ((uint32_t)0x00000080) |
Definition at line 5283 of file stm32f4xx.h.
| #define RTC_CR_FMT ((uint32_t)0x00000040) |
Definition at line 5284 of file stm32f4xx.h.
| #define RTC_CR_OSEL ((uint32_t)0x00600000) |
Definition at line 5267 of file stm32f4xx.h.
| #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
Definition at line 5268 of file stm32f4xx.h.
| #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
Definition at line 5269 of file stm32f4xx.h.
| #define RTC_CR_POL ((uint32_t)0x00100000) |
Definition at line 5270 of file stm32f4xx.h.
| #define RTC_CR_REFCKON ((uint32_t)0x00000010) |
Definition at line 5286 of file stm32f4xx.h.
| #define RTC_CR_SUB1H ((uint32_t)0x00020000) |
Definition at line 5273 of file stm32f4xx.h.
| #define RTC_CR_TSE ((uint32_t)0x00000800) |
Definition at line 5279 of file stm32f4xx.h.
| #define RTC_CR_TSEDGE ((uint32_t)0x00000008) |
Definition at line 5287 of file stm32f4xx.h.
| #define RTC_CR_TSIE ((uint32_t)0x00008000) |
Definition at line 5275 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
Definition at line 5288 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
Definition at line 5289 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
Definition at line 5290 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
Definition at line 5291 of file stm32f4xx.h.
| #define RTC_CR_WUTE ((uint32_t)0x00000400) |
Definition at line 5280 of file stm32f4xx.h.
| #define RTC_CR_WUTIE ((uint32_t)0x00004000) |
Definition at line 5276 of file stm32f4xx.h.
| #define RTC_DR_DT ((uint32_t)0x00000030) |
Definition at line 5256 of file stm32f4xx.h.
| #define RTC_DR_DT_0 ((uint32_t)0x00000010) |
Definition at line 5257 of file stm32f4xx.h.
| #define RTC_DR_DT_1 ((uint32_t)0x00000020) |
Definition at line 5258 of file stm32f4xx.h.
| #define RTC_DR_DU ((uint32_t)0x0000000F) |
Definition at line 5259 of file stm32f4xx.h.
| #define RTC_DR_DU_0 ((uint32_t)0x00000001) |
Definition at line 5260 of file stm32f4xx.h.
| #define RTC_DR_DU_1 ((uint32_t)0x00000002) |
Definition at line 5261 of file stm32f4xx.h.
| #define RTC_DR_DU_2 ((uint32_t)0x00000004) |
Definition at line 5262 of file stm32f4xx.h.
| #define RTC_DR_DU_3 ((uint32_t)0x00000008) |
Definition at line 5263 of file stm32f4xx.h.
| #define RTC_DR_MT ((uint32_t)0x00001000) |
Definition at line 5250 of file stm32f4xx.h.
| #define RTC_DR_MU ((uint32_t)0x00000F00) |
Definition at line 5251 of file stm32f4xx.h.
| #define RTC_DR_MU_0 ((uint32_t)0x00000100) |
Definition at line 5252 of file stm32f4xx.h.
| #define RTC_DR_MU_1 ((uint32_t)0x00000200) |
Definition at line 5253 of file stm32f4xx.h.
| #define RTC_DR_MU_2 ((uint32_t)0x00000400) |
Definition at line 5254 of file stm32f4xx.h.
| #define RTC_DR_MU_3 ((uint32_t)0x00000800) |
Definition at line 5255 of file stm32f4xx.h.
| #define RTC_DR_WDU ((uint32_t)0x0000E000) |
Definition at line 5246 of file stm32f4xx.h.
| #define RTC_DR_WDU_0 ((uint32_t)0x00002000) |
Definition at line 5247 of file stm32f4xx.h.
| #define RTC_DR_WDU_1 ((uint32_t)0x00004000) |
Definition at line 5248 of file stm32f4xx.h.
| #define RTC_DR_WDU_2 ((uint32_t)0x00008000) |
Definition at line 5249 of file stm32f4xx.h.
| #define RTC_DR_YT ((uint32_t)0x00F00000) |
Definition at line 5236 of file stm32f4xx.h.
| #define RTC_DR_YT_0 ((uint32_t)0x00100000) |
Definition at line 5237 of file stm32f4xx.h.
| #define RTC_DR_YT_1 ((uint32_t)0x00200000) |
Definition at line 5238 of file stm32f4xx.h.
| #define RTC_DR_YT_2 ((uint32_t)0x00400000) |
Definition at line 5239 of file stm32f4xx.h.
| #define RTC_DR_YT_3 ((uint32_t)0x00800000) |
Definition at line 5240 of file stm32f4xx.h.
| #define RTC_DR_YU ((uint32_t)0x000F0000) |
Definition at line 5241 of file stm32f4xx.h.
| #define RTC_DR_YU_0 ((uint32_t)0x00010000) |
Definition at line 5242 of file stm32f4xx.h.
| #define RTC_DR_YU_1 ((uint32_t)0x00020000) |
Definition at line 5243 of file stm32f4xx.h.
| #define RTC_DR_YU_2 ((uint32_t)0x00040000) |
Definition at line 5244 of file stm32f4xx.h.
| #define RTC_DR_YU_3 ((uint32_t)0x00080000) |
Definition at line 5245 of file stm32f4xx.h.
| #define RTC_ISR_ALRAF ((uint32_t)0x00000100) |
Definition at line 5300 of file stm32f4xx.h.
| #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
Definition at line 5308 of file stm32f4xx.h.
| #define RTC_ISR_ALRBF ((uint32_t)0x00000200) |
Definition at line 5299 of file stm32f4xx.h.
| #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
Definition at line 5307 of file stm32f4xx.h.
| #define RTC_ISR_INIT ((uint32_t)0x00000080) |
Definition at line 5301 of file stm32f4xx.h.
| #define RTC_ISR_INITF ((uint32_t)0x00000040) |
Definition at line 5302 of file stm32f4xx.h.
| #define RTC_ISR_INITS ((uint32_t)0x00000010) |
Definition at line 5304 of file stm32f4xx.h.
| #define RTC_ISR_RECALPF ((uint32_t)0x00010000) |
Definition at line 5294 of file stm32f4xx.h.
| #define RTC_ISR_RSF ((uint32_t)0x00000020) |
Definition at line 5303 of file stm32f4xx.h.
| #define RTC_ISR_SHPF ((uint32_t)0x00000008) |
Definition at line 5305 of file stm32f4xx.h.
| #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
Definition at line 5295 of file stm32f4xx.h.
| #define RTC_ISR_TSF ((uint32_t)0x00000800) |
Definition at line 5297 of file stm32f4xx.h.
| #define RTC_ISR_TSOVF ((uint32_t)0x00001000) |
Definition at line 5296 of file stm32f4xx.h.
| #define RTC_ISR_WUTF ((uint32_t)0x00000400) |
Definition at line 5298 of file stm32f4xx.h.
| #define RTC_ISR_WUTWF ((uint32_t)0x00000004) |
Definition at line 5306 of file stm32f4xx.h.
| #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
Definition at line 5311 of file stm32f4xx.h.
| #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
Definition at line 5312 of file stm32f4xx.h.
| #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
Definition at line 5413 of file stm32f4xx.h.
| #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
Definition at line 5412 of file stm32f4xx.h.
| #define RTC_SSR_SS ((uint32_t)0x0000FFFF) |
Definition at line 5409 of file stm32f4xx.h.
| #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
Definition at line 5483 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
Definition at line 5500 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
Definition at line 5499 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
Definition at line 5490 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
Definition at line 5491 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
Definition at line 5492 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
Definition at line 5493 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
Definition at line 5494 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
Definition at line 5495 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
Definition at line 5496 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
Definition at line 5498 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
Definition at line 5485 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
Definition at line 5487 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
Definition at line 5488 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
Definition at line 5489 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
Definition at line 5486 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
Definition at line 5497 of file stm32f4xx.h.
| #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
Definition at line 5484 of file stm32f4xx.h.
| #define RTC_TR_HT ((uint32_t)0x00300000) |
Definition at line 5208 of file stm32f4xx.h.
| #define RTC_TR_HT_0 ((uint32_t)0x00100000) |
Definition at line 5209 of file stm32f4xx.h.
| #define RTC_TR_HT_1 ((uint32_t)0x00200000) |
Definition at line 5210 of file stm32f4xx.h.
| #define RTC_TR_HU ((uint32_t)0x000F0000) |
Definition at line 5211 of file stm32f4xx.h.
| #define RTC_TR_HU_0 ((uint32_t)0x00010000) |
Definition at line 5212 of file stm32f4xx.h.
| #define RTC_TR_HU_1 ((uint32_t)0x00020000) |
Definition at line 5213 of file stm32f4xx.h.
| #define RTC_TR_HU_2 ((uint32_t)0x00040000) |
Definition at line 5214 of file stm32f4xx.h.
| #define RTC_TR_HU_3 ((uint32_t)0x00080000) |
Definition at line 5215 of file stm32f4xx.h.
| #define RTC_TR_MNT ((uint32_t)0x00007000) |
Definition at line 5216 of file stm32f4xx.h.
| #define RTC_TR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 5217 of file stm32f4xx.h.
| #define RTC_TR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 5218 of file stm32f4xx.h.
| #define RTC_TR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 5219 of file stm32f4xx.h.
| #define RTC_TR_MNU ((uint32_t)0x00000F00) |
Definition at line 5220 of file stm32f4xx.h.
| #define RTC_TR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 5221 of file stm32f4xx.h.
| #define RTC_TR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 5222 of file stm32f4xx.h.
| #define RTC_TR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 5223 of file stm32f4xx.h.
| #define RTC_TR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 5224 of file stm32f4xx.h.
| #define RTC_TR_PM ((uint32_t)0x00400000) |
Definition at line 5207 of file stm32f4xx.h.
| #define RTC_TR_ST ((uint32_t)0x00000070) |
Definition at line 5225 of file stm32f4xx.h.
| #define RTC_TR_ST_0 ((uint32_t)0x00000010) |
Definition at line 5226 of file stm32f4xx.h.
| #define RTC_TR_ST_1 ((uint32_t)0x00000020) |
Definition at line 5227 of file stm32f4xx.h.
| #define RTC_TR_ST_2 ((uint32_t)0x00000040) |
Definition at line 5228 of file stm32f4xx.h.
| #define RTC_TR_SU ((uint32_t)0x0000000F) |
Definition at line 5229 of file stm32f4xx.h.
| #define RTC_TR_SU_0 ((uint32_t)0x00000001) |
Definition at line 5230 of file stm32f4xx.h.
| #define RTC_TR_SU_1 ((uint32_t)0x00000002) |
Definition at line 5231 of file stm32f4xx.h.
| #define RTC_TR_SU_2 ((uint32_t)0x00000004) |
Definition at line 5232 of file stm32f4xx.h.
| #define RTC_TR_SU_3 ((uint32_t)0x00000008) |
Definition at line 5233 of file stm32f4xx.h.
| #define RTC_TSDR_DT ((uint32_t)0x00000030) |
Definition at line 5455 of file stm32f4xx.h.
| #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
Definition at line 5456 of file stm32f4xx.h.
| #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
Definition at line 5457 of file stm32f4xx.h.
| #define RTC_TSDR_DU ((uint32_t)0x0000000F) |
Definition at line 5458 of file stm32f4xx.h.
| #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
Definition at line 5459 of file stm32f4xx.h.
| #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
Definition at line 5460 of file stm32f4xx.h.
| #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
Definition at line 5461 of file stm32f4xx.h.
| #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
Definition at line 5462 of file stm32f4xx.h.
| #define RTC_TSDR_MT ((uint32_t)0x00001000) |
Definition at line 5449 of file stm32f4xx.h.
| #define RTC_TSDR_MU ((uint32_t)0x00000F00) |
Definition at line 5450 of file stm32f4xx.h.
| #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
Definition at line 5451 of file stm32f4xx.h.
| #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
Definition at line 5452 of file stm32f4xx.h.
| #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
Definition at line 5453 of file stm32f4xx.h.
| #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
Definition at line 5454 of file stm32f4xx.h.
| #define RTC_TSDR_WDU ((uint32_t)0x0000E000) |
Definition at line 5445 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
Definition at line 5446 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
Definition at line 5447 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
Definition at line 5448 of file stm32f4xx.h.
| #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
Definition at line 5465 of file stm32f4xx.h.
| #define RTC_TSTR_HT ((uint32_t)0x00300000) |
Definition at line 5417 of file stm32f4xx.h.
| #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
Definition at line 5418 of file stm32f4xx.h.
| #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
Definition at line 5419 of file stm32f4xx.h.
| #define RTC_TSTR_HU ((uint32_t)0x000F0000) |
Definition at line 5420 of file stm32f4xx.h.
| #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
Definition at line 5421 of file stm32f4xx.h.
| #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
Definition at line 5422 of file stm32f4xx.h.
| #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
Definition at line 5423 of file stm32f4xx.h.
| #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
Definition at line 5424 of file stm32f4xx.h.
| #define RTC_TSTR_MNT ((uint32_t)0x00007000) |
Definition at line 5425 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 5426 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 5427 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 5428 of file stm32f4xx.h.
| #define RTC_TSTR_MNU ((uint32_t)0x00000F00) |
Definition at line 5429 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 5430 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 5431 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 5432 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 5433 of file stm32f4xx.h.
| #define RTC_TSTR_PM ((uint32_t)0x00400000) |
Definition at line 5416 of file stm32f4xx.h.
| #define RTC_TSTR_ST ((uint32_t)0x00000070) |
Definition at line 5434 of file stm32f4xx.h.
| #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
Definition at line 5435 of file stm32f4xx.h.
| #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
Definition at line 5436 of file stm32f4xx.h.
| #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
Definition at line 5437 of file stm32f4xx.h.
| #define RTC_TSTR_SU ((uint32_t)0x0000000F) |
Definition at line 5438 of file stm32f4xx.h.
| #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
Definition at line 5439 of file stm32f4xx.h.
| #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
Definition at line 5440 of file stm32f4xx.h.
| #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
Definition at line 5441 of file stm32f4xx.h.
| #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
Definition at line 5442 of file stm32f4xx.h.
| #define RTC_WPR_KEY ((uint32_t)0x000000FF) |
Definition at line 5406 of file stm32f4xx.h.
| #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
Definition at line 5315 of file stm32f4xx.h.
| #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
Command argument
Definition at line 5602 of file stm32f4xx.h.
| #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
Clock divider bypass enable bit
Definition at line 5592 of file stm32f4xx.h.
| #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
Clock divide factor
Definition at line 5589 of file stm32f4xx.h.
| #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
Clock enable bit
Definition at line 5590 of file stm32f4xx.h.
| #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
HW Flow Control enable
Definition at line 5599 of file stm32f4xx.h.
| #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
SDIO_CK dephasing selection bit
Definition at line 5598 of file stm32f4xx.h.
| #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
Power saving configuration bit
Definition at line 5591 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
WIDBUS[1:0] bits (Wide bus mode enable bit)
Definition at line 5594 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
Bit 0
Definition at line 5595 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
Bit 1
Definition at line 5596 of file stm32f4xx.h.
| #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
CE-ATA command
Definition at line 5617 of file stm32f4xx.h.
| #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
Command Index
Definition at line 5605 of file stm32f4xx.h.
| #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
Command path state machine (CPSM) Enable bit
Definition at line 5613 of file stm32f4xx.h.
| #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
Enable CMD completion
Definition at line 5615 of file stm32f4xx.h.
| #define SDIO_CMD_NIEN ((uint16_t)0x2000) |
Not Interrupt Enable
Definition at line 5616 of file stm32f4xx.h.
| #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
SD I/O suspend command
Definition at line 5614 of file stm32f4xx.h.
| #define SDIO_CMD_WAITINT ((uint16_t)0x0100) |
CPSM Waits for Interrupt Request
Definition at line 5611 of file stm32f4xx.h.
| #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
CPSM Waits for ends of data transfer (CmdPend internal signal)
Definition at line 5612 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
WAITRESP[1:0] bits (Wait for response bits)
Definition at line 5607 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
Bit 0
Definition at line 5608 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
Bit 1
Definition at line 5609 of file stm32f4xx.h.
| #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
Data count value
Definition at line 5661 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
DBLOCKSIZE[3:0] bits (Data block size)
Definition at line 5649 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 5650 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 5651 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 5652 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 5653 of file stm32f4xx.h.
| #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
DMA enabled bit
Definition at line 5647 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
Data transfer direction selection
Definition at line 5645 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
Data transfer enabled bit
Definition at line 5644 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
Data transfer mode selection
Definition at line 5646 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
Read wait mode
Definition at line 5657 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
Read wait start
Definition at line 5655 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
Read wait stop
Definition at line 5656 of file stm32f4xx.h.
| #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
SD I/O enable functions
Definition at line 5658 of file stm32f4xx.h.
| #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
Data length value
Definition at line 5641 of file stm32f4xx.h.
| #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
Data timeout period.
Definition at line 5638 of file stm32f4xx.h.
| #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
Receive and transmit FIFO data
Definition at line 5734 of file stm32f4xx.h.
| #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
Remaining number of words to be written to or read from the FIFO
Definition at line 5731 of file stm32f4xx.h.
| #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
CCRCFAIL flag clear bit
Definition at line 5690 of file stm32f4xx.h.
| #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
CEATAEND flag clear bit
Definition at line 5702 of file stm32f4xx.h.
| #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
CMDREND flag clear bit
Definition at line 5696 of file stm32f4xx.h.
| #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
CMDSENT flag clear bit
Definition at line 5697 of file stm32f4xx.h.
| #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
CTIMEOUT flag clear bit
Definition at line 5692 of file stm32f4xx.h.
| #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
DATAEND flag clear bit
Definition at line 5698 of file stm32f4xx.h.
| #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
DBCKEND flag clear bit
Definition at line 5700 of file stm32f4xx.h.
| #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
DCRCFAIL flag clear bit
Definition at line 5691 of file stm32f4xx.h.
| #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
DTIMEOUT flag clear bit
Definition at line 5693 of file stm32f4xx.h.
| #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
RXOVERR flag clear bit
Definition at line 5695 of file stm32f4xx.h.
| #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
SDIOIT flag clear bit
Definition at line 5701 of file stm32f4xx.h.
| #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
STBITERR flag clear bit
Definition at line 5699 of file stm32f4xx.h.
| #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
TXUNDERR flag clear bit
Definition at line 5694 of file stm32f4xx.h.
| #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
Command CRC Fail Interrupt Enable
Definition at line 5705 of file stm32f4xx.h.
| #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
CE-ATA command completion signal received Interrupt Enable
Definition at line 5728 of file stm32f4xx.h.
| #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
CCommand Acting Interrupt Enable
Definition at line 5716 of file stm32f4xx.h.
| #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
Command Response Received Interrupt Enable
Definition at line 5711 of file stm32f4xx.h.
| #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
Command Sent Interrupt Enable
Definition at line 5712 of file stm32f4xx.h.
| #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
Command TimeOut Interrupt Enable
Definition at line 5707 of file stm32f4xx.h.
| #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
Data End Interrupt Enable
Definition at line 5713 of file stm32f4xx.h.
| #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
Data Block End Interrupt Enable
Definition at line 5715 of file stm32f4xx.h.
| #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
Data CRC Fail Interrupt Enable
Definition at line 5706 of file stm32f4xx.h.
| #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
Data TimeOut Interrupt Enable
Definition at line 5708 of file stm32f4xx.h.
| #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
Data receive acting interrupt enabled
Definition at line 5718 of file stm32f4xx.h.
| #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
Data available in Rx FIFO interrupt Enable
Definition at line 5726 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
Rx FIFO Empty interrupt Enable
Definition at line 5724 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
Rx FIFO Full interrupt Enable
Definition at line 5722 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
Rx FIFO Half Full interrupt Enable
Definition at line 5720 of file stm32f4xx.h.
| #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
Rx FIFO OverRun Error Interrupt Enable
Definition at line 5710 of file stm32f4xx.h.
| #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
SDIO Mode Interrupt Received interrupt Enable
Definition at line 5727 of file stm32f4xx.h.
| #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
Start Bit Error Interrupt Enable
Definition at line 5714 of file stm32f4xx.h.
| #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
Data Transmit Acting Interrupt Enable
Definition at line 5717 of file stm32f4xx.h.
| #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
Data available in Tx FIFO interrupt Enable
Definition at line 5725 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
Tx FIFO Empty interrupt Enable
Definition at line 5723 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
Tx FIFO Full interrupt Enable
Definition at line 5721 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
Tx FIFO Half Empty interrupt Enable
Definition at line 5719 of file stm32f4xx.h.
| #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
Tx FIFO UnderRun Error Interrupt Enable
Definition at line 5709 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
PWRCTRL[1:0] bits (Power supply control bits)
Definition at line 5584 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
Bit 0
Definition at line 5585 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
Bit 1
Definition at line 5586 of file stm32f4xx.h.
| #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 5623 of file stm32f4xx.h.
| #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 5626 of file stm32f4xx.h.
| #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 5629 of file stm32f4xx.h.
| #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 5632 of file stm32f4xx.h.
| #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 5635 of file stm32f4xx.h.
| #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
Response command index
Definition at line 5620 of file stm32f4xx.h.
| #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
Command response received (CRC check failed)
Definition at line 5664 of file stm32f4xx.h.
| #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
CE-ATA command completion signal received for CMD61
Definition at line 5687 of file stm32f4xx.h.
| #define SDIO_STA_CMDACT ((uint32_t)0x00000800) |
Command transfer in progress
Definition at line 5675 of file stm32f4xx.h.
| #define SDIO_STA_CMDREND ((uint32_t)0x00000040) |
Command response received (CRC check passed)
Definition at line 5670 of file stm32f4xx.h.
| #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
Command sent (no response required)
Definition at line 5671 of file stm32f4xx.h.
| #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
Command response timeout
Definition at line 5666 of file stm32f4xx.h.
| #define SDIO_STA_DATAEND ((uint32_t)0x00000100) |
Data end (data counter, SDIDCOUNT, is zero)
Definition at line 5672 of file stm32f4xx.h.
| #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
Data block sent/received (CRC check passed)
Definition at line 5674 of file stm32f4xx.h.
| #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
Data block sent/received (CRC check failed)
Definition at line 5665 of file stm32f4xx.h.
| #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
Data timeout
Definition at line 5667 of file stm32f4xx.h.
| #define SDIO_STA_RXACT ((uint32_t)0x00002000) |
Data receive in progress
Definition at line 5677 of file stm32f4xx.h.
| #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
Data available in receive FIFO
Definition at line 5685 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
Receive FIFO empty
Definition at line 5683 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
Receive FIFO full
Definition at line 5681 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
Receive FIFO Half Full: there are at least 8 words in the FIFO
Definition at line 5679 of file stm32f4xx.h.
| #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
Received FIFO overrun error
Definition at line 5669 of file stm32f4xx.h.
| #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
SDIO interrupt received
Definition at line 5686 of file stm32f4xx.h.
| #define SDIO_STA_STBITERR ((uint32_t)0x00000200) |
Start bit not detected on all data signals in wide bus mode
Definition at line 5673 of file stm32f4xx.h.
| #define SDIO_STA_TXACT ((uint32_t)0x00001000) |
Data transmit in progress
Definition at line 5676 of file stm32f4xx.h.
| #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
Data available in transmit FIFO
Definition at line 5684 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
Transmit FIFO empty
Definition at line 5682 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
Transmit FIFO full
Definition at line 5680 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
Transmit FIFO Half Empty: at least 8 words can be written into the FIFO
Definition at line 5678 of file stm32f4xx.h.
| #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
Transmit FIFO underrun error
Definition at line 5668 of file stm32f4xx.h.
| #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
Bidirectional data mode enable
Definition at line 5760 of file stm32f4xx.h.
| #define SPI_CR1_BIDIOE ((uint16_t)0x4000) |
Output enable in bidirectional mode
Definition at line 5759 of file stm32f4xx.h.
| #define SPI_CR1_BR ((uint16_t)0x0038) |
BR[2:0] bits (Baud Rate Control)
Definition at line 5746 of file stm32f4xx.h.
| #define SPI_CR1_BR_0 ((uint16_t)0x0008) |
Bit 0
Definition at line 5747 of file stm32f4xx.h.
| #define SPI_CR1_BR_1 ((uint16_t)0x0010) |
Bit 1
Definition at line 5748 of file stm32f4xx.h.
| #define SPI_CR1_BR_2 ((uint16_t)0x0020) |
Bit 2
Definition at line 5749 of file stm32f4xx.h.
| #define SPI_CR1_CPHA ((uint16_t)0x0001) |
Clock Phase
Definition at line 5742 of file stm32f4xx.h.
| #define SPI_CR1_CPOL ((uint16_t)0x0002) |
Clock Polarity
Definition at line 5743 of file stm32f4xx.h.
| #define SPI_CR1_CRCEN ((uint16_t)0x2000) |
Hardware CRC calculation enable
Definition at line 5758 of file stm32f4xx.h.
| #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
Transmit CRC next
Definition at line 5757 of file stm32f4xx.h.
| #define SPI_CR1_DFF ((uint16_t)0x0800) |
Data Frame Format
Definition at line 5756 of file stm32f4xx.h.
| #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
Frame Format
Definition at line 5752 of file stm32f4xx.h.
| #define SPI_CR1_MSTR ((uint16_t)0x0004) |
Master Selection
Definition at line 5744 of file stm32f4xx.h.
| #define SPI_CR1_RXONLY ((uint16_t)0x0400) |
Receive only
Definition at line 5755 of file stm32f4xx.h.
| #define SPI_CR1_SPE ((uint16_t)0x0040) |
SPI Enable
Definition at line 5751 of file stm32f4xx.h.
| #define SPI_CR1_SSI ((uint16_t)0x0100) |
Internal slave select
Definition at line 5753 of file stm32f4xx.h.
| #define SPI_CR1_SSM ((uint16_t)0x0200) |
Software slave management
Definition at line 5754 of file stm32f4xx.h.
| #define SPI_CR2_ERRIE ((uint8_t)0x20) |
Error Interrupt Enable
Definition at line 5766 of file stm32f4xx.h.
| #define SPI_CR2_RXDMAEN ((uint8_t)0x01) |
Rx Buffer DMA Enable
Definition at line 5763 of file stm32f4xx.h.
| #define SPI_CR2_RXNEIE ((uint8_t)0x40) |
RX buffer Not Empty Interrupt Enable
Definition at line 5767 of file stm32f4xx.h.
| #define SPI_CR2_SSOE ((uint8_t)0x04) |
SS Output Enable
Definition at line 5765 of file stm32f4xx.h.
| #define SPI_CR2_TXDMAEN ((uint8_t)0x02) |
Tx Buffer DMA Enable
Definition at line 5764 of file stm32f4xx.h.
| #define SPI_CR2_TXEIE ((uint8_t)0x80) |
Tx buffer Empty Interrupt Enable
Definition at line 5768 of file stm32f4xx.h.
| #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
CRC polynomial register
Definition at line 5784 of file stm32f4xx.h.
| #define SPI_DR_DR ((uint16_t)0xFFFF) |
Data Register
Definition at line 5781 of file stm32f4xx.h.
| #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
Channel length (number of bits per audio channel)
Definition at line 5793 of file stm32f4xx.h.
| #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
steady state clock polarity
Definition at line 5799 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
DATLEN[1:0] bits (Data length to be transferred)
Definition at line 5795 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
Bit 0
Definition at line 5796 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
Bit 1
Definition at line 5797 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
I2SCFG[1:0] bits (I2S configuration mode)
Definition at line 5807 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 5808 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 5809 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
I2S Enable
Definition at line 5811 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
I2S mode selection
Definition at line 5812 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
I2SSTD[1:0] bits (I2S standard selection)
Definition at line 5801 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 5802 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 5803 of file stm32f4xx.h.
| #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
PCM frame synchronization
Definition at line 5805 of file stm32f4xx.h.
| #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
I2S Linear prescaler
Definition at line 5815 of file stm32f4xx.h.
| #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
Master Clock Output Enable
Definition at line 5817 of file stm32f4xx.h.
| #define SPI_I2SPR_ODD ((uint16_t)0x0100) |
Odd factor for the prescaler
Definition at line 5816 of file stm32f4xx.h.
| #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
Rx CRC Register
Definition at line 5787 of file stm32f4xx.h.
| #define SPI_SR_BSY ((uint8_t)0x80) |
Busy flag
Definition at line 5778 of file stm32f4xx.h.
| #define SPI_SR_CHSIDE ((uint8_t)0x04) |
Channel side
Definition at line 5773 of file stm32f4xx.h.
| #define SPI_SR_CRCERR ((uint8_t)0x10) |
CRC Error flag
Definition at line 5775 of file stm32f4xx.h.
| #define SPI_SR_MODF ((uint8_t)0x20) |
Mode fault
Definition at line 5776 of file stm32f4xx.h.
| #define SPI_SR_OVR ((uint8_t)0x40) |
Overrun flag
Definition at line 5777 of file stm32f4xx.h.
| #define SPI_SR_RXNE ((uint8_t)0x01) |
Receive buffer Not Empty
Definition at line 5771 of file stm32f4xx.h.
| #define SPI_SR_TXE ((uint8_t)0x02) |
Transmit buffer Empty
Definition at line 5772 of file stm32f4xx.h.
| #define SPI_SR_UDR ((uint8_t)0x08) |
Underrun flag
Definition at line 5774 of file stm32f4xx.h.
| #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
Tx CRC Register
Definition at line 5790 of file stm32f4xx.h.
| #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
Compensation cell ready flag
Definition at line 6048 of file stm32f4xx.h.
| #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
Compensation cell power-down
Definition at line 6049 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
EXTI 0 configuration
Definition at line 5835 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
PB[0] pin
Definition at line 5843 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
PC[0] pin
Definition at line 5844 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
PD[0] pin
Definition at line 5845 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
PE[0] pin
Definition at line 5846 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
PF[0] pin
Definition at line 5847 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
PG[0] pin
Definition at line 5848 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
PH[0] pin
Definition at line 5849 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
PI[0] pin
Definition at line 5850 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
EXTI 1 configuration
Definition at line 5836 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
PB[1] pin
Definition at line 5855 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
PC[1] pin
Definition at line 5856 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
PD[1] pin
Definition at line 5857 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
PE[1] pin
Definition at line 5858 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
PF[1] pin
Definition at line 5859 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
PG[1] pin
Definition at line 5860 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
PH[1] pin
Definition at line 5861 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
PI[1] pin
Definition at line 5862 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
EXTI 2 configuration
Definition at line 5837 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
PB[2] pin
Definition at line 5867 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
PC[2] pin
Definition at line 5868 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
PD[2] pin
Definition at line 5869 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
PE[2] pin
Definition at line 5870 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
PF[2] pin
Definition at line 5871 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
PG[2] pin
Definition at line 5872 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
PH[2] pin
Definition at line 5873 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
PI[2] pin
Definition at line 5874 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
EXTI 3 configuration
Definition at line 5838 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
PB[3] pin
Definition at line 5879 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
PC[3] pin
Definition at line 5880 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
PD[3] pin
Definition at line 5881 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
PE[3] pin
Definition at line 5882 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
PF[3] pin
Definition at line 5883 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
PG[3] pin
Definition at line 5884 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
PH[3] pin
Definition at line 5885 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
PI[3] pin
Definition at line 5886 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
EXTI 4 configuration
Definition at line 5889 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
PB[4] pin
Definition at line 5897 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
PC[4] pin
Definition at line 5898 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
PD[4] pin
Definition at line 5899 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
PE[4] pin
Definition at line 5900 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
PF[4] pin
Definition at line 5901 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
PG[4] pin
Definition at line 5902 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
PH[4] pin
Definition at line 5903 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
PI[4] pin
Definition at line 5904 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
EXTI 5 configuration
Definition at line 5890 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
PB[5] pin
Definition at line 5909 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
PC[5] pin
Definition at line 5910 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
PD[5] pin
Definition at line 5911 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
PE[5] pin
Definition at line 5912 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
PF[5] pin
Definition at line 5913 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
PG[5] pin
Definition at line 5914 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
PH[5] pin
Definition at line 5915 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
PI[5] pin
Definition at line 5916 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
EXTI 6 configuration
Definition at line 5891 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
PB[6] pin
Definition at line 5921 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
PC[6] pin
Definition at line 5922 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
PD[6] pin
Definition at line 5923 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
PE[6] pin
Definition at line 5924 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
PF[6] pin
Definition at line 5925 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
PG[6] pin
Definition at line 5926 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
PH[6] pin
Definition at line 5927 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
PI[6] pin
Definition at line 5928 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
EXTI 7 configuration
Definition at line 5892 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
PB[7] pin
Definition at line 5933 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
PC[7] pin
Definition at line 5934 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
PD[7] pin
Definition at line 5935 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
PE[7] pin
Definition at line 5936 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
PF[7] pin
Definition at line 5937 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
PG[7] pin
Definition at line 5938 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
PH[7] pin
Definition at line 5939 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
PI[7] pin
Definition at line 5940 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
EXTI 10 configuration
Definition at line 5945 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
PB[10] pin
Definition at line 5976 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
PC[10] pin
Definition at line 5977 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
PD[10] pin
Definition at line 5978 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
PE[10] pin
Definition at line 5979 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
PF[10] pin
Definition at line 5980 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
PG[10] pin
Definition at line 5981 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
PH[10] pin
Definition at line 5982 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
PI[10] pin
Definition at line 5983 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
EXTI 11 configuration
Definition at line 5946 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
PB[11] pin
Definition at line 5988 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
PC[11] pin
Definition at line 5989 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
PD[11] pin
Definition at line 5990 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
PE[11] pin
Definition at line 5991 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
PF[11] pin
Definition at line 5992 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
PG[11] pin
Definition at line 5993 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
PH[11] pin
Definition at line 5994 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
PI[11] pin
Definition at line 5995 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) |
PH[12] pin
Definition at line 6012 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) |
PH[13] pin
Definition at line 6023 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) |
PH[14] pin
Definition at line 6034 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) |
PH[15] pin
Definition at line 6045 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
EXTI 8 configuration
Definition at line 5943 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
PB[8] pin
Definition at line 5952 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
PC[8] pin
Definition at line 5953 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
PD[8] pin
Definition at line 5954 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
PE[8] pin
Definition at line 5955 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
PF[8] pin
Definition at line 5956 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
PG[8] pin
Definition at line 5957 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
PH[8] pin
Definition at line 5958 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
PI[8] pin
Definition at line 5959 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
EXTI 9 configuration
Definition at line 5944 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
PB[9] pin
Definition at line 5964 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
PC[9] pin
Definition at line 5965 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
PD[9] pin
Definition at line 5966 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
PE[9] pin
Definition at line 5967 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
PF[9] pin
Definition at line 5968 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
PG[9] pin
Definition at line 5969 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
PH[9] pin
Definition at line 5970 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
PI[9] pin
Definition at line 5971 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
EXTI 12 configuration
Definition at line 5998 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
PB[12] pin
Definition at line 6006 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
PC[12] pin
Definition at line 6007 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
PD[12] pin
Definition at line 6008 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
PE[12] pin
Definition at line 6009 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
PF[12] pin
Definition at line 6010 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
PG[12] pin
Definition at line 6011 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
EXTI 13 configuration
Definition at line 5999 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
PB[13] pin
Definition at line 6017 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
PC[13] pin
Definition at line 6018 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
PD[13] pin
Definition at line 6019 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
PE[13] pin
Definition at line 6020 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
PF[13] pin
Definition at line 6021 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
PG[13] pin
Definition at line 6022 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
EXTI 14 configuration
Definition at line 6000 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
PB[14] pin
Definition at line 6028 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
PC[14] pin
Definition at line 6029 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
PD[14] pin
Definition at line 6030 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
PE[14] pin
Definition at line 6031 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
PF[14] pin
Definition at line 6032 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
PG[14] pin
Definition at line 6033 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
EXTI 15 configuration
Definition at line 6001 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
PB[15] pin
Definition at line 6039 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
PC[15] pin
Definition at line 6040 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
PD[15] pin
Definition at line 6041 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
PE[15] pin
Definition at line 6042 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
PF[15] pin
Definition at line 6043 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
PG[15] pin
Definition at line 6044 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) |
SYSCFG_Memory Remap Config
Definition at line 5825 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
Definition at line 5826 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
Definition at line 5827 of file stm32f4xx.h.
| #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
Definition at line 5832 of file stm32f4xx.h.
| #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
Ethernet PHY interface selection
Definition at line 5830 of file stm32f4xx.h.
| #define TIM_ARR_ARR ((uint16_t)0xFFFF) |
actual auto-reload Value
Definition at line 6285 of file stm32f4xx.h.
| #define TIM_BDTR_AOE ((uint16_t)0x4000) |
Automatic Output enable
Definition at line 6321 of file stm32f4xx.h.
| #define TIM_BDTR_BKE ((uint16_t)0x1000) |
Break enable
Definition at line 6319 of file stm32f4xx.h.
| #define TIM_BDTR_BKP ((uint16_t)0x2000) |
Break Polarity
Definition at line 6320 of file stm32f4xx.h.
| #define TIM_BDTR_DTG ((uint16_t)0x00FF) |
DTG[0:7] bits (Dead-Time Generator set-up)
Definition at line 6303 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6304 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6305 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 6306 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 6307 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 6308 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 6309 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
Bit 6
Definition at line 6310 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
Bit 7
Definition at line 6311 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK ((uint16_t)0x0300) |
LOCK[1:0] bits (Lock Configuration)
Definition at line 6313 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6314 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6315 of file stm32f4xx.h.
| #define TIM_BDTR_MOE ((uint16_t)0x8000) |
Main Output enable
Definition at line 6322 of file stm32f4xx.h.
| #define TIM_BDTR_OSSI ((uint16_t)0x0400) |
Off-State Selection for Idle mode
Definition at line 6317 of file stm32f4xx.h.
| #define TIM_BDTR_OSSR ((uint16_t)0x0800) |
Off-State Selection for Run mode
Definition at line 6318 of file stm32f4xx.h.
| #define TIM_CCER_CC1E ((uint16_t)0x0001) |
Capture/Compare 1 output enable
Definition at line 6262 of file stm32f4xx.h.
| #define TIM_CCER_CC1NE ((uint16_t)0x0004) |
Capture/Compare 1 Complementary output enable
Definition at line 6264 of file stm32f4xx.h.
| #define TIM_CCER_CC1NP ((uint16_t)0x0008) |
Capture/Compare 1 Complementary output Polarity
Definition at line 6265 of file stm32f4xx.h.
| #define TIM_CCER_CC1P ((uint16_t)0x0002) |
Capture/Compare 1 output Polarity
Definition at line 6263 of file stm32f4xx.h.
| #define TIM_CCER_CC2E ((uint16_t)0x0010) |
Capture/Compare 2 output enable
Definition at line 6266 of file stm32f4xx.h.
| #define TIM_CCER_CC2NE ((uint16_t)0x0040) |
Capture/Compare 2 Complementary output enable
Definition at line 6268 of file stm32f4xx.h.
| #define TIM_CCER_CC2NP ((uint16_t)0x0080) |
Capture/Compare 2 Complementary output Polarity
Definition at line 6269 of file stm32f4xx.h.
| #define TIM_CCER_CC2P ((uint16_t)0x0020) |
Capture/Compare 2 output Polarity
Definition at line 6267 of file stm32f4xx.h.
| #define TIM_CCER_CC3E ((uint16_t)0x0100) |
Capture/Compare 3 output enable
Definition at line 6270 of file stm32f4xx.h.
| #define TIM_CCER_CC3NE ((uint16_t)0x0400) |
Capture/Compare 3 Complementary output enable
Definition at line 6272 of file stm32f4xx.h.
| #define TIM_CCER_CC3NP ((uint16_t)0x0800) |
Capture/Compare 3 Complementary output Polarity
Definition at line 6273 of file stm32f4xx.h.
| #define TIM_CCER_CC3P ((uint16_t)0x0200) |
Capture/Compare 3 output Polarity
Definition at line 6271 of file stm32f4xx.h.
| #define TIM_CCER_CC4E ((uint16_t)0x1000) |
Capture/Compare 4 output enable
Definition at line 6274 of file stm32f4xx.h.
| #define TIM_CCER_CC4NP ((uint16_t)0x8000) |
Capture/Compare 4 Complementary output Polarity
Definition at line 6276 of file stm32f4xx.h.
| #define TIM_CCER_CC4P ((uint16_t)0x2000) |
Capture/Compare 4 output Polarity
Definition at line 6275 of file stm32f4xx.h.
| #define TIM_CCMR1_CC1S ((uint16_t)0x0003) |
CC1S[1:0] bits (Capture/Compare 1 Selection)
Definition at line 6160 of file stm32f4xx.h.
| #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6161 of file stm32f4xx.h.
| #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6162 of file stm32f4xx.h.
| #define TIM_CCMR1_CC2S ((uint16_t)0x0300) |
CC2S[1:0] bits (Capture/Compare 2 Selection)
Definition at line 6174 of file stm32f4xx.h.
| #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6175 of file stm32f4xx.h.
| #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6176 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
IC1F[3:0] bits (Input Capture 1 Filter)
Definition at line 6194 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6195 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6196 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6197 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 6198 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
IC1PSC[1:0] bits (Input Capture 1 Prescaler)
Definition at line 6190 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
Bit 0
Definition at line 6191 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
Bit 1
Definition at line 6192 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F ((uint16_t)0xF000) |
IC2F[3:0] bits (Input Capture 2 Filter)
Definition at line 6204 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6205 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6206 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 6207 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
Bit 3
Definition at line 6208 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
IC2PSC[1:0] bits (Input Capture 2 Prescaler)
Definition at line 6200 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 6201 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 6202 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
Output Compare 1Clear Enable
Definition at line 6172 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
Output Compare 1 Fast enable
Definition at line 6164 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M ((uint16_t)0x0070) |
OC1M[2:0] bits (Output Compare 1 Mode)
Definition at line 6167 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6168 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6169 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6170 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
Output Compare 1 Preload enable
Definition at line 6165 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
Output Compare 2 Clear Enable
Definition at line 6186 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
Output Compare 2 Fast enable
Definition at line 6178 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M ((uint16_t)0x7000) |
OC2M[2:0] bits (Output Compare 2 Mode)
Definition at line 6181 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6182 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6183 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 6184 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
Output Compare 2 Preload enable
Definition at line 6179 of file stm32f4xx.h.
| #define TIM_CCMR2_CC3S ((uint16_t)0x0003) |
CC3S[1:0] bits (Capture/Compare 3 Selection)
Definition at line 6211 of file stm32f4xx.h.
| #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6212 of file stm32f4xx.h.
| #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6213 of file stm32f4xx.h.
| #define TIM_CCMR2_CC4S ((uint16_t)0x0300) |
CC4S[1:0] bits (Capture/Compare 4 Selection)
Definition at line 6225 of file stm32f4xx.h.
| #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6226 of file stm32f4xx.h.
| #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6227 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
IC3F[3:0] bits (Input Capture 3 Filter)
Definition at line 6245 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6246 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6247 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6248 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 6249 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
IC3PSC[1:0] bits (Input Capture 3 Prescaler)
Definition at line 6241 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
Bit 0
Definition at line 6242 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
Bit 1
Definition at line 6243 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F ((uint16_t)0xF000) |
IC4F[3:0] bits (Input Capture 4 Filter)
Definition at line 6255 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6256 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6257 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 6258 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
Bit 3
Definition at line 6259 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
IC4PSC[1:0] bits (Input Capture 4 Prescaler)
Definition at line 6251 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 6252 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 6253 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
Output Compare 3 Clear Enable
Definition at line 6223 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
Output Compare 3 Fast enable
Definition at line 6215 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M ((uint16_t)0x0070) |
OC3M[2:0] bits (Output Compare 3 Mode)
Definition at line 6218 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6219 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6220 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6221 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
Output Compare 3 Preload enable
Definition at line 6216 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
Output Compare 4 Clear Enable
Definition at line 6237 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
Output Compare 4 Fast enable
Definition at line 6229 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M ((uint16_t)0x7000) |
OC4M[2:0] bits (Output Compare 4 Mode)
Definition at line 6232 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6233 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6234 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 6235 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
Output Compare 4 Preload enable
Definition at line 6230 of file stm32f4xx.h.
| #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
Capture/Compare 1 Value
Definition at line 6291 of file stm32f4xx.h.
| #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
Capture/Compare 2 Value
Definition at line 6294 of file stm32f4xx.h.
| #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
Capture/Compare 3 Value
Definition at line 6297 of file stm32f4xx.h.
| #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
Capture/Compare 4 Value
Definition at line 6300 of file stm32f4xx.h.
| #define TIM_CNT_CNT ((uint16_t)0xFFFF) |
Counter Value
Definition at line 6279 of file stm32f4xx.h.
| #define TIM_CR1_ARPE ((uint16_t)0x0080) |
Auto-reload preload enable
Definition at line 6067 of file stm32f4xx.h.
| #define TIM_CR1_CEN ((uint16_t)0x0001) |
Counter enable
Definition at line 6057 of file stm32f4xx.h.
| #define TIM_CR1_CKD ((uint16_t)0x0300) |
CKD[1:0] bits (clock division)
Definition at line 6069 of file stm32f4xx.h.
| #define TIM_CR1_CKD_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6070 of file stm32f4xx.h.
| #define TIM_CR1_CKD_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6071 of file stm32f4xx.h.
| #define TIM_CR1_CMS ((uint16_t)0x0060) |
CMS[1:0] bits (Center-aligned mode selection)
Definition at line 6063 of file stm32f4xx.h.
| #define TIM_CR1_CMS_0 ((uint16_t)0x0020) |
Bit 0
Definition at line 6064 of file stm32f4xx.h.
| #define TIM_CR1_CMS_1 ((uint16_t)0x0040) |
Bit 1
Definition at line 6065 of file stm32f4xx.h.
| #define TIM_CR1_DIR ((uint16_t)0x0010) |
Direction
Definition at line 6061 of file stm32f4xx.h.
| #define TIM_CR1_OPM ((uint16_t)0x0008) |
One pulse mode
Definition at line 6060 of file stm32f4xx.h.
| #define TIM_CR1_UDIS ((uint16_t)0x0002) |
Update disable
Definition at line 6058 of file stm32f4xx.h.
| #define TIM_CR1_URS ((uint16_t)0x0004) |
Update request source
Definition at line 6059 of file stm32f4xx.h.
| #define TIM_CR2_CCDS ((uint16_t)0x0008) |
Capture/Compare DMA Selection
Definition at line 6076 of file stm32f4xx.h.
| #define TIM_CR2_CCPC ((uint16_t)0x0001) |
Capture/Compare Preloaded Control
Definition at line 6074 of file stm32f4xx.h.
| #define TIM_CR2_CCUS ((uint16_t)0x0004) |
Capture/Compare Control Update Selection
Definition at line 6075 of file stm32f4xx.h.
| #define TIM_CR2_MMS ((uint16_t)0x0070) |
MMS[2:0] bits (Master Mode Selection)
Definition at line 6078 of file stm32f4xx.h.
| #define TIM_CR2_MMS_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6079 of file stm32f4xx.h.
| #define TIM_CR2_MMS_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6080 of file stm32f4xx.h.
| #define TIM_CR2_MMS_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6081 of file stm32f4xx.h.
| #define TIM_CR2_OIS1 ((uint16_t)0x0100) |
Output Idle state 1 (OC1 output)
Definition at line 6084 of file stm32f4xx.h.
| #define TIM_CR2_OIS1N ((uint16_t)0x0200) |
Output Idle state 1 (OC1N output)
Definition at line 6085 of file stm32f4xx.h.
| #define TIM_CR2_OIS2 ((uint16_t)0x0400) |
Output Idle state 2 (OC2 output)
Definition at line 6086 of file stm32f4xx.h.
| #define TIM_CR2_OIS2N ((uint16_t)0x0800) |
Output Idle state 2 (OC2N output)
Definition at line 6087 of file stm32f4xx.h.
| #define TIM_CR2_OIS3 ((uint16_t)0x1000) |
Output Idle state 3 (OC3 output)
Definition at line 6088 of file stm32f4xx.h.
| #define TIM_CR2_OIS3N ((uint16_t)0x2000) |
Output Idle state 3 (OC3N output)
Definition at line 6089 of file stm32f4xx.h.
| #define TIM_CR2_OIS4 ((uint16_t)0x4000) |
Output Idle state 4 (OC4 output)
Definition at line 6090 of file stm32f4xx.h.
| #define TIM_CR2_TI1S ((uint16_t)0x0080) |
TI1 Selection
Definition at line 6083 of file stm32f4xx.h.
| #define TIM_DCR_DBA ((uint16_t)0x001F) |
DBA[4:0] bits (DMA Base Address)
Definition at line 6325 of file stm32f4xx.h.
| #define TIM_DCR_DBA_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6326 of file stm32f4xx.h.
| #define TIM_DCR_DBA_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6327 of file stm32f4xx.h.
| #define TIM_DCR_DBA_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 6328 of file stm32f4xx.h.
| #define TIM_DCR_DBA_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 6329 of file stm32f4xx.h.
| #define TIM_DCR_DBA_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 6330 of file stm32f4xx.h.
| #define TIM_DCR_DBL ((uint16_t)0x1F00) |
DBL[4:0] bits (DMA Burst Length)
Definition at line 6332 of file stm32f4xx.h.
| #define TIM_DCR_DBL_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6333 of file stm32f4xx.h.
| #define TIM_DCR_DBL_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6334 of file stm32f4xx.h.
| #define TIM_DCR_DBL_2 ((uint16_t)0x0400) |
Bit 2
Definition at line 6335 of file stm32f4xx.h.
| #define TIM_DCR_DBL_3 ((uint16_t)0x0800) |
Bit 3
Definition at line 6336 of file stm32f4xx.h.
| #define TIM_DCR_DBL_4 ((uint16_t)0x1000) |
Bit 4
Definition at line 6337 of file stm32f4xx.h.
| #define TIM_DIER_BIE ((uint16_t)0x0080) |
Break interrupt enable
Definition at line 6126 of file stm32f4xx.h.
| #define TIM_DIER_CC1DE ((uint16_t)0x0200) |
Capture/Compare 1 DMA request enable
Definition at line 6128 of file stm32f4xx.h.
| #define TIM_DIER_CC1IE ((uint16_t)0x0002) |
Capture/Compare 1 interrupt enable
Definition at line 6120 of file stm32f4xx.h.
| #define TIM_DIER_CC2DE ((uint16_t)0x0400) |
Capture/Compare 2 DMA request enable
Definition at line 6129 of file stm32f4xx.h.
| #define TIM_DIER_CC2IE ((uint16_t)0x0004) |
Capture/Compare 2 interrupt enable
Definition at line 6121 of file stm32f4xx.h.
| #define TIM_DIER_CC3DE ((uint16_t)0x0800) |
Capture/Compare 3 DMA request enable
Definition at line 6130 of file stm32f4xx.h.
| #define TIM_DIER_CC3IE ((uint16_t)0x0008) |
Capture/Compare 3 interrupt enable
Definition at line 6122 of file stm32f4xx.h.
| #define TIM_DIER_CC4DE ((uint16_t)0x1000) |
Capture/Compare 4 DMA request enable
Definition at line 6131 of file stm32f4xx.h.
| #define TIM_DIER_CC4IE ((uint16_t)0x0010) |
Capture/Compare 4 interrupt enable
Definition at line 6123 of file stm32f4xx.h.
| #define TIM_DIER_COMDE ((uint16_t)0x2000) |
COM DMA request enable
Definition at line 6132 of file stm32f4xx.h.
| #define TIM_DIER_COMIE ((uint16_t)0x0020) |
COM interrupt enable
Definition at line 6124 of file stm32f4xx.h.
| #define TIM_DIER_TDE ((uint16_t)0x4000) |
Trigger DMA request enable
Definition at line 6133 of file stm32f4xx.h.
| #define TIM_DIER_TIE ((uint16_t)0x0040) |
Trigger interrupt enable
Definition at line 6125 of file stm32f4xx.h.
| #define TIM_DIER_UDE ((uint16_t)0x0100) |
Update DMA request enable
Definition at line 6127 of file stm32f4xx.h.
| #define TIM_DIER_UIE ((uint16_t)0x0001) |
Update interrupt enable
Definition at line 6119 of file stm32f4xx.h.
| #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
DMA register for burst accesses
Definition at line 6340 of file stm32f4xx.h.
| #define TIM_EGR_BG ((uint8_t)0x80) |
Break Generation
Definition at line 6157 of file stm32f4xx.h.
| #define TIM_EGR_CC1G ((uint8_t)0x02) |
Capture/Compare 1 Generation
Definition at line 6151 of file stm32f4xx.h.
| #define TIM_EGR_CC2G ((uint8_t)0x04) |
Capture/Compare 2 Generation
Definition at line 6152 of file stm32f4xx.h.
| #define TIM_EGR_CC3G ((uint8_t)0x08) |
Capture/Compare 3 Generation
Definition at line 6153 of file stm32f4xx.h.
| #define TIM_EGR_CC4G ((uint8_t)0x10) |
Capture/Compare 4 Generation
Definition at line 6154 of file stm32f4xx.h.
| #define TIM_EGR_COMG ((uint8_t)0x20) |
Capture/Compare Control Update Generation
Definition at line 6155 of file stm32f4xx.h.
| #define TIM_EGR_TG ((uint8_t)0x40) |
Trigger Generation
Definition at line 6156 of file stm32f4xx.h.
| #define TIM_EGR_UG ((uint8_t)0x01) |
Update Generation
Definition at line 6150 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)
Definition at line 6346 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 6347 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 6348 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
TI4_RMP[1:0] bits (TIM5 Input 4 remap)
Definition at line 6343 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
Bit 0
Definition at line 6344 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
Bit 1
Definition at line 6345 of file stm32f4xx.h.
| #define TIM_PSC_PSC ((uint16_t)0xFFFF) |
Prescaler Value
Definition at line 6282 of file stm32f4xx.h.
| #define TIM_RCR_REP ((uint8_t)0xFF) |
Repetition Counter Value
Definition at line 6288 of file stm32f4xx.h.
| #define TIM_SMCR_ECE ((uint16_t)0x4000) |
External clock enable
Definition at line 6115 of file stm32f4xx.h.
| #define TIM_SMCR_ETF ((uint16_t)0x0F00) |
ETF[3:0] bits (External trigger filter)
Definition at line 6105 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 6106 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 6107 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
Bit 2
Definition at line 6108 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
Bit 3
Definition at line 6109 of file stm32f4xx.h.
| #define TIM_SMCR_ETP ((uint16_t)0x8000) |
External trigger polarity
Definition at line 6116 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS ((uint16_t)0x3000) |
ETPS[1:0] bits (External trigger prescaler)
Definition at line 6111 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6112 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6113 of file stm32f4xx.h.
| #define TIM_SMCR_MSM ((uint16_t)0x0080) |
Master/slave mode
Definition at line 6103 of file stm32f4xx.h.
| #define TIM_SMCR_SMS ((uint16_t)0x0007) |
SMS[2:0] bits (Slave mode selection)
Definition at line 6093 of file stm32f4xx.h.
| #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6094 of file stm32f4xx.h.
| #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6095 of file stm32f4xx.h.
| #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 6096 of file stm32f4xx.h.
| #define TIM_SMCR_TS ((uint16_t)0x0070) |
TS[2:0] bits (Trigger selection)
Definition at line 6098 of file stm32f4xx.h.
| #define TIM_SMCR_TS_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 6099 of file stm32f4xx.h.
| #define TIM_SMCR_TS_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 6100 of file stm32f4xx.h.
| #define TIM_SMCR_TS_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 6101 of file stm32f4xx.h.
| #define TIM_SR_BIF ((uint16_t)0x0080) |
Break interrupt Flag
Definition at line 6143 of file stm32f4xx.h.
| #define TIM_SR_CC1IF ((uint16_t)0x0002) |
Capture/Compare 1 interrupt Flag
Definition at line 6137 of file stm32f4xx.h.
| #define TIM_SR_CC1OF ((uint16_t)0x0200) |
Capture/Compare 1 Overcapture Flag
Definition at line 6144 of file stm32f4xx.h.
| #define TIM_SR_CC2IF ((uint16_t)0x0004) |
Capture/Compare 2 interrupt Flag
Definition at line 6138 of file stm32f4xx.h.
| #define TIM_SR_CC2OF ((uint16_t)0x0400) |
Capture/Compare 2 Overcapture Flag
Definition at line 6145 of file stm32f4xx.h.
| #define TIM_SR_CC3IF ((uint16_t)0x0008) |
Capture/Compare 3 interrupt Flag
Definition at line 6139 of file stm32f4xx.h.
| #define TIM_SR_CC3OF ((uint16_t)0x0800) |
Capture/Compare 3 Overcapture Flag
Definition at line 6146 of file stm32f4xx.h.
| #define TIM_SR_CC4IF ((uint16_t)0x0010) |
Capture/Compare 4 interrupt Flag
Definition at line 6140 of file stm32f4xx.h.
| #define TIM_SR_CC4OF ((uint16_t)0x1000) |
Capture/Compare 4 Overcapture Flag
Definition at line 6147 of file stm32f4xx.h.
| #define TIM_SR_COMIF ((uint16_t)0x0020) |
COM interrupt Flag
Definition at line 6141 of file stm32f4xx.h.
| #define TIM_SR_TIF ((uint16_t)0x0040) |
Trigger interrupt Flag
Definition at line 6142 of file stm32f4xx.h.
| #define TIM_SR_UIF ((uint16_t)0x0001) |
Update interrupt Flag
Definition at line 6136 of file stm32f4xx.h.
| #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
Fraction of USARTDIV
Definition at line 6372 of file stm32f4xx.h.
| #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
Mantissa of USARTDIV
Definition at line 6373 of file stm32f4xx.h.
| #define USART_CR1_IDLEIE ((uint16_t)0x0010) |
IDLE Interrupt Enable
Definition at line 6380 of file stm32f4xx.h.
| #define USART_CR1_M ((uint16_t)0x1000) |
Word length
Definition at line 6388 of file stm32f4xx.h.
| #define USART_CR1_OVER8 ((uint16_t)0x8000) |
USART Oversampling by 8 enable
Definition at line 6390 of file stm32f4xx.h.
| #define USART_CR1_PCE ((uint16_t)0x0400) |
Parity Control Enable
Definition at line 6386 of file stm32f4xx.h.
| #define USART_CR1_PEIE ((uint16_t)0x0100) |
PE Interrupt Enable
Definition at line 6384 of file stm32f4xx.h.
| #define USART_CR1_PS ((uint16_t)0x0200) |
Parity Selection
Definition at line 6385 of file stm32f4xx.h.
| #define USART_CR1_RE ((uint16_t)0x0004) |
Receiver Enable
Definition at line 6378 of file stm32f4xx.h.
| #define USART_CR1_RWU ((uint16_t)0x0002) |
Receiver wakeup
Definition at line 6377 of file stm32f4xx.h.
| #define USART_CR1_RXNEIE ((uint16_t)0x0020) |
RXNE Interrupt Enable
Definition at line 6381 of file stm32f4xx.h.
| #define USART_CR1_SBK ((uint16_t)0x0001) |
Send Break
Definition at line 6376 of file stm32f4xx.h.
| #define USART_CR1_TCIE ((uint16_t)0x0040) |
Transmission Complete Interrupt Enable
Definition at line 6382 of file stm32f4xx.h.
| #define USART_CR1_TE ((uint16_t)0x0008) |
Transmitter Enable
Definition at line 6379 of file stm32f4xx.h.
| #define USART_CR1_TXEIE ((uint16_t)0x0080) |
PE Interrupt Enable
Definition at line 6383 of file stm32f4xx.h.
| #define USART_CR1_UE ((uint16_t)0x2000) |
USART Enable
Definition at line 6389 of file stm32f4xx.h.
| #define USART_CR1_WAKE ((uint16_t)0x0800) |
Wakeup method
Definition at line 6387 of file stm32f4xx.h.
| #define USART_CR2_ADD ((uint16_t)0x000F) |
Address of the USART node
Definition at line 6393 of file stm32f4xx.h.
| #define USART_CR2_CLKEN ((uint16_t)0x0800) |
Clock Enable
Definition at line 6399 of file stm32f4xx.h.
| #define USART_CR2_CPHA ((uint16_t)0x0200) |
Clock Phase
Definition at line 6397 of file stm32f4xx.h.
| #define USART_CR2_CPOL ((uint16_t)0x0400) |
Clock Polarity
Definition at line 6398 of file stm32f4xx.h.
| #define USART_CR2_LBCL ((uint16_t)0x0100) |
Last Bit Clock pulse
Definition at line 6396 of file stm32f4xx.h.
| #define USART_CR2_LBDIE ((uint16_t)0x0040) |
LIN Break Detection Interrupt Enable
Definition at line 6395 of file stm32f4xx.h.
| #define USART_CR2_LBDL ((uint16_t)0x0020) |
LIN Break Detection Length
Definition at line 6394 of file stm32f4xx.h.
| #define USART_CR2_LINEN ((uint16_t)0x4000) |
LIN mode enable
Definition at line 6405 of file stm32f4xx.h.
| #define USART_CR2_STOP ((uint16_t)0x3000) |
STOP[1:0] bits (STOP bits)
Definition at line 6401 of file stm32f4xx.h.
| #define USART_CR2_STOP_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 6402 of file stm32f4xx.h.
| #define USART_CR2_STOP_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 6403 of file stm32f4xx.h.
| #define USART_CR3_CTSE ((uint16_t)0x0200) |
CTS Enable
Definition at line 6417 of file stm32f4xx.h.
| #define USART_CR3_CTSIE ((uint16_t)0x0400) |
CTS Interrupt Enable
Definition at line 6418 of file stm32f4xx.h.
| #define USART_CR3_DMAR ((uint16_t)0x0040) |
DMA Enable Receiver
Definition at line 6414 of file stm32f4xx.h.
| #define USART_CR3_DMAT ((uint16_t)0x0080) |
DMA Enable Transmitter
Definition at line 6415 of file stm32f4xx.h.
| #define USART_CR3_EIE ((uint16_t)0x0001) |
Error Interrupt Enable
Definition at line 6408 of file stm32f4xx.h.
| #define USART_CR3_HDSEL ((uint16_t)0x0008) |
Half-Duplex Selection
Definition at line 6411 of file stm32f4xx.h.
| #define USART_CR3_IREN ((uint16_t)0x0002) |
IrDA mode Enable
Definition at line 6409 of file stm32f4xx.h.
| #define USART_CR3_IRLP ((uint16_t)0x0004) |
IrDA Low-Power
Definition at line 6410 of file stm32f4xx.h.
| #define USART_CR3_NACK ((uint16_t)0x0010) |
Smartcard NACK enable
Definition at line 6412 of file stm32f4xx.h.
| #define USART_CR3_ONEBIT ((uint16_t)0x0800) |
USART One bit method enable
Definition at line 6419 of file stm32f4xx.h.
| #define USART_CR3_RTSE ((uint16_t)0x0100) |
RTS Enable
Definition at line 6416 of file stm32f4xx.h.
| #define USART_CR3_SCEN ((uint16_t)0x0020) |
Smartcard mode enable
Definition at line 6413 of file stm32f4xx.h.
| #define USART_DR_DR ((uint16_t)0x01FF) |
Data value
Definition at line 6369 of file stm32f4xx.h.
| #define USART_GTPR_GT ((uint16_t)0xFF00) |
Guard time value
Definition at line 6432 of file stm32f4xx.h.
| #define USART_GTPR_PSC ((uint16_t)0x00FF) |
PSC[7:0] bits (Prescaler value)
Definition at line 6422 of file stm32f4xx.h.
| #define USART_GTPR_PSC_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6423 of file stm32f4xx.h.
| #define USART_GTPR_PSC_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6424 of file stm32f4xx.h.
| #define USART_GTPR_PSC_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 6425 of file stm32f4xx.h.
| #define USART_GTPR_PSC_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 6426 of file stm32f4xx.h.
| #define USART_GTPR_PSC_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 6427 of file stm32f4xx.h.
| #define USART_GTPR_PSC_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 6428 of file stm32f4xx.h.
| #define USART_GTPR_PSC_6 ((uint16_t)0x0040) |
Bit 6
Definition at line 6429 of file stm32f4xx.h.
| #define USART_GTPR_PSC_7 ((uint16_t)0x0080) |
Bit 7
Definition at line 6430 of file stm32f4xx.h.
| #define USART_SR_CTS ((uint16_t)0x0200) |
CTS Flag
Definition at line 6366 of file stm32f4xx.h.
| #define USART_SR_FE ((uint16_t)0x0002) |
Framing Error
Definition at line 6358 of file stm32f4xx.h.
| #define USART_SR_IDLE ((uint16_t)0x0010) |
IDLE line detected
Definition at line 6361 of file stm32f4xx.h.
| #define USART_SR_LBD ((uint16_t)0x0100) |
LIN Break Detection Flag
Definition at line 6365 of file stm32f4xx.h.
| #define USART_SR_NE ((uint16_t)0x0004) |
Noise Error Flag
Definition at line 6359 of file stm32f4xx.h.
| #define USART_SR_ORE ((uint16_t)0x0008) |
OverRun Error
Definition at line 6360 of file stm32f4xx.h.
| #define USART_SR_PE ((uint16_t)0x0001) |
Parity Error
Definition at line 6357 of file stm32f4xx.h.
| #define USART_SR_RXNE ((uint16_t)0x0020) |
Read Data Register Not Empty
Definition at line 6362 of file stm32f4xx.h.
| #define USART_SR_TC ((uint16_t)0x0040) |
Transmission Complete
Definition at line 6363 of file stm32f4xx.h.
| #define USART_SR_TXE ((uint16_t)0x0080) |
Transmit Data Register Empty
Definition at line 6364 of file stm32f4xx.h.
| #define WWDG_CFR_EWI ((uint16_t)0x0200) |
Early Wakeup Interrupt
Definition at line 6465 of file stm32f4xx.h.
| #define WWDG_CFR_W ((uint16_t)0x007F) |
W[6:0] bits (7-bit window value)
Definition at line 6452 of file stm32f4xx.h.
| #define WWDG_CFR_W0 ((uint16_t)0x0001) |
Bit 0
Definition at line 6453 of file stm32f4xx.h.
| #define WWDG_CFR_W1 ((uint16_t)0x0002) |
Bit 1
Definition at line 6454 of file stm32f4xx.h.
| #define WWDG_CFR_W2 ((uint16_t)0x0004) |
Bit 2
Definition at line 6455 of file stm32f4xx.h.
| #define WWDG_CFR_W3 ((uint16_t)0x0008) |
Bit 3
Definition at line 6456 of file stm32f4xx.h.
| #define WWDG_CFR_W4 ((uint16_t)0x0010) |
Bit 4
Definition at line 6457 of file stm32f4xx.h.
| #define WWDG_CFR_W5 ((uint16_t)0x0020) |
Bit 5
Definition at line 6458 of file stm32f4xx.h.
| #define WWDG_CFR_W6 ((uint16_t)0x0040) |
Bit 6
Definition at line 6459 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB ((uint16_t)0x0180) |
WDGTB[1:0] bits (Timer Base)
Definition at line 6461 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
Bit 0
Definition at line 6462 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
Bit 1
Definition at line 6463 of file stm32f4xx.h.
| #define WWDG_CR_T ((uint8_t)0x7F) |
T[6:0] bits (7-Bit counter (MSB to LSB))
Definition at line 6440 of file stm32f4xx.h.
| #define WWDG_CR_T0 ((uint8_t)0x01) |
Bit 0
Definition at line 6441 of file stm32f4xx.h.
| #define WWDG_CR_T1 ((uint8_t)0x02) |
Bit 1
Definition at line 6442 of file stm32f4xx.h.
| #define WWDG_CR_T2 ((uint8_t)0x04) |
Bit 2
Definition at line 6443 of file stm32f4xx.h.
| #define WWDG_CR_T3 ((uint8_t)0x08) |
Bit 3
Definition at line 6444 of file stm32f4xx.h.
| #define WWDG_CR_T4 ((uint8_t)0x10) |
Bit 4
Definition at line 6445 of file stm32f4xx.h.
| #define WWDG_CR_T5 ((uint8_t)0x20) |
Bit 5
Definition at line 6446 of file stm32f4xx.h.
| #define WWDG_CR_T6 ((uint8_t)0x40) |
Bit 6
Definition at line 6447 of file stm32f4xx.h.
| #define WWDG_CR_WDGA ((uint8_t)0x80) |
Activation bit
Definition at line 6449 of file stm32f4xx.h.
| #define WWDG_SR_EWIF ((uint8_t)0x01) |
Early Wakeup Interrupt Flag
Definition at line 6468 of file stm32f4xx.h.